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| 8 - channel, low noise, low power, 24 - bit, sigma - delta adc with pga and reference data sheet ad7124 - 8 rev. b document feedback information furnished by analog devices is believed to be ac curate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is gra nted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 analog devices, inc. all rights reserved. technical support www.analog.com features 3 p ower m odes rms n oise low p ower: 24 nv rms at 1.17 sps , gain = 128 (2 5 5 a typ ical ) mid p ower: 20 nv rms at 2.34 sps , gain = 128 (3 5 5 a typ ical ) full p ower: 23 nv rms at 9. 4 sps , gain = 128 ( 9 30 a typ ical ) up to 22 n oise f ree bits in all power modes (gain = 1) output data rate full power : 9.38 sps to 19,2 00 sps mid power : 2.34 sps to 48 00 sps low power : 1.17 sps to 24 00 sps rail - to - r ail a nalog i nputs for gains > 1 simultaneous 50 hz/60 hz rejection at 25 sps (single cycle settling) diag nostic f unctions (which aid safe integrity level (sil ) certification) crosspoint mu ltiplex ed analog inputs 8 differential/15 pseudo differential inputs p rogra mmable gain (1 to 128) band gap referenc e with 15 ppm/c drift max imum (65 a) matched p rogrammable e xcit ation c urrents internal clock oscillator on - chip bias voltage generator low - side power switch general - p urpose o utputs multiple filter o ptions internal t emperature s ensor self and s ystem c alibration sensor b urnout d etection automatic c hannel s equencer per c hannel c onfiguration power supply: 2.7 v to 3.6 v and 1.8 v independent interface power supply power - down current : 5 a maximum temperature range: ? 40 c to +105c 32- lead lfcsp 3 - wire or 4 - wire serial interface spi, qspi?, m icrowire?, and dsp compatibl e schmitt trigger on sclk esd: 4 kv applications temperature measurement pressure measurement industrial process control instrumentation smart transmitters functional block dia gram temper a ture sensor bandga p ref v bias seria l inter f ace and contro l logic interna l clock clk sclk din sync regcapd iov dd ad7124-8 a v ss dgnd 24-bit - adc x-mux refin1(+) a v dd a v ss refout a v dd a v ss psw v ariable digi t a l fi l ter diagnostics communic a tions power supp l y signa l chain digi t a l refin1(?) refin2(+) refin2(?) burnout detect exci ta tion currents power switch gpos channe l sequencer crosspoint mux regca p a a v dd 1.9v ldo diagnostics a v dd a v ss av ss dout/rd y cs 1.8v ldo ain0/iout/vbias analog buffers reference buffers ain1/iout/vbias ain2/iout/vbias/p1 ain3/iout/vbias/p2 ain4/iout/vbias/p3 ain5/iout/vbias/p4 ain6/iout/vbias ain7/iout/vbias ain8/iout/vbias ain9/iout/vbias ain10/iout/vbias ain 1 1/iout/vbias ain12/iout/vbias ain13/iout/vbias ain14/iout/vbias/refin2(+) ain15/iout/vbias/refin2(?) buf buf pga2 pga1 13048-001 figure 1.
ad7124- 8 data sheet rev. b | page 2 of 91 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 3 general description ......................................................................... 4 specifications ..................................................................................... 5 timing characteristics .............................................................. 10 absolute maximum ratings .......................................................... 13 thermal resistance .................................................................... 13 esd caution ................................................................................ 13 pin configuration and function descriptions ........................... 14 terminology .................................................................................... 17 typical performance characteristics ........................................... 18 rms noise and resolution ............................................................ 27 full power mode ......................................................................... 27 mid power mode ........................................................................ 30 low power mode ........................................................................ 33 getting started ................................................................................ 36 overview ...................................................................................... 36 power supplies ............................................................................ 37 digital communication ............................................................. 37 configuration overview ........................................................... 39 adc circuit information .............................................................. 44 analog input channel ............................................................... 44 programmable gain array (pga) ........................................... 45 reference ..................................................................................... 45 bipolar/unipolar configuration .............................................. 46 data output coding .................................................................. 46 excitation currents .................................................................... 46 bridge power - down switch ...................................................... 46 logic outputs .............................................................................. 47 bias voltage generator .............................................................. 47 clock ............................................................................................ 47 power modes ............................................................................... 47 standby and power - down modes ............................................ 48 digital interface .......................................................................... 48 data_status .......................................................................... 50 serial interface reset (dout_ rdy _del and cs _en bits) 50 reset ............................................................................................. 50 calibration ................................................................................... 51 span and offset limits .............................................................. 52 system synchronization ............................................................ 52 digital filter .................................................................................... 53 sinc 4 filter ................................................................................... 53 sinc 3 filter ................................................................................... 55 fast settling mode (sinc 4 + sinc 1 filter) .................................. 57 fast settling mode (sinc 3 + sinc 1 filter) .................................. 59 post filters ................................................................................... 61 summary of filter options ....................................................... 64 diagnostics ...................................................................................... 65 signal chain check .................................................................... 65 reference detect ......................................................................... 65 calibration, conversion, and saturation errors .................... 65 overvoltage/undervoltage detection ..................................... 65 power supply monitors ............................................................. 66 ldo monito ring ........................................................................ 66 mclk counter ........................................................................... 66 spi sclk counter ...................................................................... 66 spi read/write errors ............................................................... 67 spi_ignore error ................................................................... 67 checksum protection ................................................................ 67 memory map checksum pr otection ....................................... 67 burnout currents ....................................................................... 69 temperature sensor ................................................................... 69 grounding and layout .................................................................. 70 applications information .............................................................. 71 temperature measurement using a thermocouple .............. 71 temperature measurement using an rtd ............................. 72 flowmeter .................................................................................... 74 on - chip registers .......................................................................... 76 communications register ......................................................... 77 status register ............................................................................. 77 adc_control register ....................................................... 78 data register ............................................................................... 80 io_control_1 register ........................................................ 80 io_control_2 register ........................................................ 82 id register ................................................................................... 83 error register .............................................................................. 83 error_en register ................................................................. 84 mclk_count register .......................................................... 85 data sheet ad7124- 8 rev. b | page 3 of 91 channel registers ........................................................................ 86 configuration registers ............................................................. 88 filter registers ............................................................................. 89 offset registers ............................................................................ 90 gain registers .............................................................................. 90 outline dimensions ........................................................................ 91 ordering guide ........................................................................... 91 revision history 7 /15 rev. a to rev. b change s to figure 29 ...................................................................... 21 ch ange to single conversion mode section ............................... 4 9 changes to calibration section ..................................................... 51 changes to figure 82 ...................................................................... 53 changes to figure 90 ...................................................................... 56 changes to figure 98 ...................................................................... 58 changes to figure 104 .................................................................... 60 changes to reference detect section and figure 118 ................ 65 changes to table 70 ........................................................................ 83 changes to table 71 ................................ ................................ ................. 8 4 changes to table 75 ........................................................................ 89 5/15 rev. 0 to rev. a changes to temperature measurement using a thermocoupl e section .............................................................................................. 7 1 change d ainm to ainp, table 70 ............................................... 8 3 change d refout to internal reference, t able 73 ................... 8 6 4 /15 revision 0 : initial version ad7124-8 data sheet rev. b | page 4 of 91 general description th e ad7124 -8 is a low power, low noise, complete ly integrated an alog front end for high precisio n measurement applications. the device contain s a low noise, 24 - bi t - analog - to -digital converter ( adc ) , and can be configured to have 8 differential inputs or 15 single- ended or pseudo differential inputs. the on - chip low gain stage e nsure s that signals of small amplitude can be interfaced directly to the adc. one of t he major advantages of the ad7124 -8 is that it gives the user the flexibility to employ one of three integrated power modes. the current consumption, range of outp ut data rates , and rms noise can be tailored with the power mode selected. the device also offers a multitude of filter options , ensuring that the user has the highest degree of flexibility. the ad7124 -8 can achieve simul tane ous 50 hz and 60 hz rejection when operating at an output data rate of 25 sps (single cycle settling) , with rejection in excess of 80 db achieved at lower output data rates. the ad7124 -8 e stablishes the highest degree of signal chain integration. the device c ontains a precision, low noise, low drift internal band gap reference and accepts an external differential reference , which c an be internally buffered . other key integrated features inc lude programmable low drift excitation current sources, burnout currents , and a bias voltage generator , which set s the common - mode voltage of a channel to av dd /2. the low - side power switch enables the user to power down bridge sensors between conversions, ensuring the absolute minimal power consumption of the system. the device also allows the user the option of operating with either an internal clock or an external clock . the integrated chan nel sequencer allows several channels to be enabled simultaneously , and the ad7124 -8 sequentially converts on each enabled channel, simplifying communication with the device. as many as 16 channels can be enabled at any time, a channel b eing defined as an an alog i nput or a d iagnostic s uch as a p ower supply c heck or a reference check. this un ique feature a llows diagnostics to be interleaved w ith c onversions. the ad7124 -8 also su pports per c hanne l configuration. t he device a llows eight configurations or setups. e ach c onfiguration consist s o f ga in, f ilter ty pe, o utput data r ate, b uffering, and refere nce source. the u ser c an a ssign any of the se setup s on a channel b y channel basis. t he ad7124 -8 also has extensive diagnostic functionality integrated as part of its comprehensive feature set. these diagnostics include a cyclic redundancy check ( crc ), signal chain checks, and serial interface checks , which lead to a more robust solution. these diagnostics reduce the need for external components to implement diagnostics , resulting in reduced bo ard space needs, reduced design cycle times, and cost savings . the failure modes effects and diagnostic analysis (fmeda ) of a typical application has shown a safe failure fraction (sff) greater than 90% according to iec 61508. the device operates with a single analog power supply from 2.7 v to 3.6 v or a dual 1.8 v power supply. the digital supply has a ran ge of 1.65 v to 3.6 v. it is specified for a temperature range of ? 40 c to +105 c . the ad7124 -8 is housed in a 32 - lead lfcsp package. note that , throughout this data sheet, multifunction pins, such as dout/ rdy , are referred to either by the entire pin name or by a single function of the pin, for example, rdy , when only that function is relevant. t able 1 . ad7124 -8 overview parameter low power mode mid power mode full power mode maximum output data rate 2400 sps 4800 sps 19,200 sps rms noise ( g ain = 128) 24 nv 20 nv 23 nv p eak -to -p eak res olution at 1200 sps (gain = 1) 16.4 bits 17.1 bits 18 bits typical current (adc + pga) 25 5 a 35 5 a 9 30 a data sheet ad7124- 8 rev. b | page 5 of 91 specifications av dd = 2. 9 v to 3.6 v ( f ull p ower m ode) , 2.7 v to 3.6 v ( m id and l ow p ower m ode) , io v dd = 1.65 v to 3.6 v, av ss = dgnd = 0 v, refinx(+ ) = 2.5 v, r e f i n x ( ? ) = av ss , all specifications t min to t max , unless otherwise noted. table 2 . parameter 1 min typ max unit test conditions/comments adc output data rate, f adc low power mode 1.17 2400 sps mid power mode 2.34 4800 sp s full power mode 9.38 19 , 200 sps no missing codes 2 24 bits fs 3 > 2, sinc 4 filter 24 bits fs 3 > 8, sinc 3 filter resolution see the rms noise and reso lution section rms noise and update rates see the rms noise and resolution section integral nonlinearity (inl) low power mode 2 ? 4 1 +4 ppm of fsr gain = 1 ? 15 2 +15 ppm of fsr gain > 1 , t a = ? 40c to +85c ? 20 2 +20 ppm of fsr gain > 1 , t a = ? 40c to + 10 5c mid power mode 2 ? 4 1 +4 ppm of fsr gain = 1 ? 15 2 +15 ppm of fsr gain > 1 full power mode ? 4 1 +4 ppm of fsr gain = 1 2 ? 15 2 +15 ppm of fsr gain > 1 offset error 4 before calibration 15 v gain = 1 to 8 200/gain v gain = 16 to 128 after i nternal cal ibration / s ystem calibration in order of n oise offset error drift vs. temperature 5 low power mode 10 nv/c gain = 1 or gain > 16 80 nv/c gain = 2 to 8 40 nv/c gain = 16 mid power mode 10 nv/c gain = 1 or gain > 16 40 nv/c gai n = 2 to 8 20 nv/c gain = 16 full power mode 10 nv/c gain error 4 , 6 before i nternal calibration ? 0.0025 +0.0025 % gain = 1, t a = 25c ? 0.3 % gain > 1 after i nternal c alibration ? 0.016 + 0.004 +0.016 % gain = 2 to 8 , t a = 25c 0.025 % gain = 16 to 128 after s ystem c alibration in order of n oise gain error drift vs. temperature 1 2 p pm/c power supply rejection a in = 1 v/gain, external reference low power mode 84 db gain = 2 to 16 91 db gain = 1 or g ain > 16 mid power mode 2 89 db gain = 2 to 16 95 db gain = 1 or g ain > 16 full power mode 96 db ad7124- 8 data sheet rev. b | page 6 of 91 parameter 1 min typ max unit test conditions/comments common - mode rejection 7 at dc 2 85 90 db a in = 1 v, gain = 1 at dc 100 105 db a in = 1 v/gain, gain 2 or 4 110 115 db a in = 1 v/gain, gain 8 sinc 3 , sinc 4 filter 2 at 50 hz, 60 hz 120 db 10 sps , 50 hz 1 hz, 60 hz 1 hz at 50 hz 120 db 50 sps , 50 hz 1 hz at 60 hz 120 db 60 sps , 60 hz 1 hz fast settling filters 2 at 50 hz 115 db first notch at 50 hz, 50 hz 1 hz at 60 hz 115 db first notch at 60 hz, 60 hz 1 hz post filters 2 at 50 hz, 60 hz 130 db 20 sps , 50 hz 1 hz , 60 hz 1 hz 130 db 25 sps , 50 hz 1 hz , 60 hz 1 hz normal mode rejection 2 sinc 4 filter external clock at 50 hz, 60 hz 120 db 10 sps , 50 hz 1 hz , 60 hz 1 hz 82 db 50 sps , rej60 8 =1, 50 hz 1 hz , 60 hz 1 hz at 50 hz 120 db 50 sps , 50 hz 1 hz at 60 hz 120 db 60 sps , 60 hz 1 hz internal clock at 50 hz, 60 hz 98 db 10 sps , 50 hz 1 hz , 60 hz 1 hz 66 db 50 sps , rej6 0 8 = 1, 50 hz 1 hz , 60 hz 1 hz at 50 hz 92 db 50 sps , 50 hz 1 hz at 60 hz 92 db 60 sps , 60 hz 1 hz sinc 3 filter external clock at 50 hz, 60 hz 100 db 10 sps , 50 hz 1 hz , 60 hz 1 hz 66 db 50 sps , rej60 8 = 1, 50 hz 1 hz , 60 hz 1 hz at 50 hz 100 db 50 sps , 50 hz 1 hz at 60 hz 100 db 60 sps , 60 hz 1 hz internal clock at 50 hz, 60 hz 73 db 10 sps , 50 hz 1 hz , 60 hz 1 hz 52 db 50 sps , rej60 8 = 1, 50 hz 1 hz , 60 hz 1 hz at 50 hz 68 db 50 sps , 50 hz 1 hz at 60 hz 68 db 60 sps , 60 hz 1 hz fast settling filters external cl ock at 50 hz 40 db first notch at 50 hz, 50 hz 0.5 hz at 60 hz 40 db first notch at 60 hz, 60 hz 0.5 hz internal clock at 50 hz 24.5 db first notch at 50 hz, 50 hz 0.5 hz at 60 hz 24.5 db first notch at 60 hz, 60 hz 0.5 h z post filters external clock at 50 hz, 60 hz 86 db 20 sps , 50 hz 1 hz , 60 hz 1 hz 62 db 25 sps , 50 hz 1 hz , 60 hz 1 hz internal clock at 50 hz, 60 hz 67 db 20 sps , 50 hz 1 hz , 60 hz 1 hz 50 db 25 sps , 50 h z 1 hz , 60 hz 1 hz data sheet ad7124- 8 rev. b | page 7 of 91 parameter 1 min typ max unit test conditions/comments analog inputs 9 differential input voltage ranges 10 v ref /gain v v ref = refin x (+) ? refin x (?), or internal reference absolute a in voltage limits 2 gain = 1 ( u nbuffered) av ss ? 0.05 av dd + 0.05 v gain = 1 ( b uffered) av ss + 0.1 av dd ? 0.1 v gain > 1 av ss ? 0.05 av dd + 0.05 v analog input current gain > 1 or gain = 1 ( b uffered) low power mode absolute input current 1 na differential input current 0. 2 na analog input current drift 2 5 pa/c mid power mode absolute input current 1.2 na differential input current 0. 4 na analog input current drift 2 5 pa/c full power mode absolute input current 3.3 na differential input current 1.5 na analog input current drift 2 5 pa/c gain = 1 ( u nbuffered) current varies with input voltage absolute input current 2.65 a/v analog input current drift 1.1 na/v /c reference input intern al reference initial accuracy 2.5 ? 0.2% 2.5 2.5 + 0.2% v t a = 25c drift 2 8 ppm/c t a = 25c to 105c 2 15 ppm/c t a = ? 40c to + 105c output current 10 ma load regulation 50 v/ma power supply rejection 85 db external referenc e external refin voltage 2 1 2.5 av dd v refin = refin x (+) ? refin x ( ? ) absolute refin voltage limits 2 av ss ? 0.05 av dd + 0.05 v unbuffered av ss + 0.1 av dd ? 0.1 v buffered reference input current buffered low power mode absolute input current 0.5 na reference input current drift 10 pa/c mid power mode absolute input current 1 na reference input current d rift 10 pa/c full power mode absolute input current 3 na reference input current drift 10 pa/c unbuffered absolute input current 12 a reference input current drift 6 na/c normal mode rejection same as for analog inputs common - mode rejection 100 db ad7124- 8 data sheet rev. b | page 8 of 91 parameter 1 min typ max unit test conditions/comments excitation current sources (i out0 / iout1 ) available on any analog input pin output current 50/100/250/ 500/750/1000 a initial tolerance 4 % t a = 25c drift 50 ppm/c current matching 0.5 % matching between iout0 and iout1 , v out = 0 v drift matching 5 30 ppm/c line regulation ( av dd ) 2 %/v av dd = 3 v 5% load regulation 0.2 %/v output compliance 2 av ss ? 0.05 av dd ? 0.3 7 v 50 a /100 a /250 a /500 a current sources , 2% accuracy av ss ? 0.05 av dd ? 0.48 v 750 a and 1000 a current sources , 2% accuracy bias v oltage (v bias ) gene rator available on any analog input pin v bias av ss + (av dd ? av ss )/2 v v bias gene rator start - up time 6.7 s/nf dependent on the capacitance connected to ain temperature sensor accuracy 0.5 c sensitivity 13, 584 codes/c low - side power switch on resistance ( r on ) 7 10 ? allowable current 2 30 ma continuous current burnout currents a in current 0.5/2/4 a analog inputs must be buffered digital outputs (p1 to p4) output voltage high , v oh av dd ? 0.6 v i source = 100 a low , v o l 0.4 v i sink = 100 a diagnostics power supply monitor detect level analog low dropout regulator (aldo) 1.6 v av dd ? av ss 2.7 v digital ldo (dldo) 1.55 v iov dd 1.75 v reference detect level 0.7 1 v ref_det_err bit active if v r ef < 0.7 v ainm/ainp overvoltage detect level av dd + 0.04 v ainm/ainp undervoltage detect level av ss ? 0.04 v internal/external clock internal clock frequency 614.4 ? 5% 614.4 614.4 + 5% khz duty cycle 50:50 % external clock frequency 2.4576 mhz internal d ivide by 4 duty cycle range 45:55 to 55:45 % logic inputs 2 input voltage low , v inl 0.3 iov dd v 1.65 v iov dd < 1.9 v 0.35 iov dd v 1.9 v iov dd < 2.3 v 0.7 v 2.3 v iov dd 3.6 v high, v inh 0.7 iov dd v 1.65 v iov dd < 1.9 v 0.65 iov dd v 1.9 v iov dd < 2.3 v 1.7 v 2.3 v iov dd < 2.7 v 2 v 2.7 v iov dd 3.6 v hysteresis 0.2 0.6 v 1.65 v iov dd 3.6 v input currents ? 1 +1 a v in = iov dd or gnd input capacitance 10 pf all digital inputs data sheet ad7124- 8 rev. b | page 9 of 91 parameter 1 min typ max unit test conditions/comments logic output s (including clk) output voltage 2 high, v oh iov dd ? 0.35 v i source = 100 a lo w, v ol 0.4 v i sink = 100 a floating state leakage current ? 1 +1 a floating state output capacitance 10 pf data output coding offset binary system calibration 2 calibration limit full - scale 1.05 fs v zero - scale ?1.05 fs v input span 0.8 fs 2.1 fs v power supply voltages for all power modes av dd to av ss low power mode 2.7 3.6 v mid power mode 2.7 3.6 v full power mode 2.9 3.6 v iov dd to gnd 1.65 3.6 v av ss to gnd ? 1.8 0 +1.8 v iov dd to av ss 5.4 v power supply currents 9 , 11 i avdd , external reference low power mode gain = 1 2 125 135 a all buffers off gain = 1 i avdd inc rease per ain b uffer 2 1 5 20 a gain = 2 to 8 205 235 a gain = 16 to 128 235 280 a i avdd increase per r ef erence buffer 2 1 0 15 a all gains m id power mode gain = 1 2 150 165 a all buffers off gain = 1 i avdd increase per ain buffer 2 30 35 a gain = 2 to 8 275 325 a gain = 16 to 1 28 330 405 a i avdd increase per reference buffer 2 2 0 30 a all gains full power mode gain = 1 2 315 345 a all buffers off gain = 1 i avdd increase per ain buffer 2 9 0 125 a gain = 2 to 8 660 790 a gain = 16 to 128 875 1100 a i avdd increase per reference buffer 2 8 5 110 a all g ains i avdd increase d ue to i nternal reference 2 50 65 a independent of power mode; t he reference buffers are not required when using this reference d ue to v bias 2 1 5 20 a independent of power mode d ue to diagnostics 2 4 5 a i iovdd low power m ode 2 0 35 a mid power m ode 2 5 40 a full power m ode 5 5 85 a ad7124- 8 data sheet rev. b | page 10 of 91 parameter 1 min typ max unit test conditions/comments power - down currents 11 independent of power mode standby current i avdd 7 12 a ldos on only i iovdd 8 17 a power - d own current i avdd 1 3 a i iovdd 1 2 a 1 temperature range = ?40c to +105c. 2 these specification s are not production tested but are supported by characterization data at the initial product release. 3 fs is the decimal equivalent of the fs [ 10: 0 ] bits in the filter register s. 4 following a sys tem or internal zero - scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. a sys tem full - scale calibration reduces the gain error to the order of the noise for the programmed gain and outpu t data rate. 5 recalibration at any temperature removes these errors. 6 gain error applies to both positive and negative full - scale. a factory calibration is performed at gain = 1, t a = 25c. 7 when gain > 1, the common - mode voltage is between (av ss + 0.1 + 0.1/gain) and (av dd ? 0.1 ? 0.5/gain). 8 rej60 is a bit in the filter registers. when the first notch of the sinc filter is at 50 hz, a notch is placed at 60 hz when rej60 is set to 1. this gives simultaneous 50 hz and 60 hz rejection. 9 when the gain is greater than 1, the analog input buffers are enabled automatically. the buffers can only be disabled when the gain equals 1. 10 when v ref = (av dd ? av ss ), the typical differential input equals 0.92 v ref /gain for the low and mid power modes and 0.86 v re f /gain for full power mode. 11 the digital inputs are equal to iov dd or d gnd with excitation currents and bias voltage generator disabled. timing characteristi cs av dd = 2. 9 v to 3.6 v (full power mod e), 2.7 v to 3.6 v (mid and low power mode) , io v dd = 1.65 v to 3.6 v, av ss = dgnd = 0 v, input logic 0 = 0 v, input logic 1 = iov dd , unless otherwise noted. table 3 . parameter 1 , 2 min typ max unit test conditions/comments t 3 100 ns sclk high pulse width t 4 100 ns sclk low pulse width t 12 delay between consecutive read/write operations 3/ mclk 3 ns full p ower m ode 12/mclk ns mid p ower m ode 24/mclk ns low p ower m ode t 13 s dout/ rd y high time if dout/ rdy is low and the next conversion is available 6 s full power mode 25 s mid power mode 50 s low power mode t 14 sync low pulse width 3/mclk ns full power mode 12 /mclk ns mid power mode 24/mclk ns low power mode r ead o peration t 1 0 80 ns cs falling edge to dout/ rdy active time t 2 4 0 80 ns sclk active edge 5 to data valid delay t 5 6 , 7 10 80 ns bus re linquish time after cs inactive edge t 6 0 ns sclk inactive edge to cs inactive edge t 7 8 sclk inactive edge to dout/ rdy high 10 ns the dout_ rdy _del bit is cleared, the cs _en bit is cleared 110 ns the dout_ rdy _del bit is set , the cs _en bit is cleared t 7 a 7 t 5 ns data valid after cs inactive edge , the cs _en bit is set data sheet ad7124- 8 rev. b | page 11 of 91 parameter 1 , 2 min typ max unit test conditions/comments write operation t 8 0 ns cs falling edge to sclk active edge 5 setup time t 9 30 ns data valid to sclk edge setup time t 10 25 ns da ta valid to sclk edge hold time t 1 1 0 ns cs rising edge to sclk edge hold time 1 these specifications were s ample tested during the initial release to ensure compliance. all input signals are speci fied with t r = t f = 5 ns (10% to 90% of iov dd and timed from a voltage level of iov dd /2. 2 see figure 3 , figure 4 , figure 5 , and figure 6 . 3 mclk is the master clock frequency. 4 these specifications are measured with the load circuit shown in figure 2 and defined as the time required for the output to cross the v ol or v oh limits. 5 t he sclk active edge is the falling edge of sclk. 6 these specifications are derived from the measured time taken by the data output to change by 0.5 v when loaded with the circ uit shown in figure 2 . the measured num ber is then extrapolated back to remove the effects of charging or discharging the 25 pf capacitor. the times quoted in the t iming characteristics are the true bus relinquish times of the device and, therefore, are independent of external bus loading capac itances. 7 rdy returns high after a read of the adc. in single conversion mode and continuous conversion mode, the same data can be read aga in, if required, while rdy is high, although subsequent reads must not occur close to the next output update. in continuous read mode, the digital word can be read only once. 8 when the cs _en bit is cleared, the dout/ rdy pin changes from its dout function to its rdy function, following the last inactive edge of the sclk. when cs _en is set, the dout pin continues to output the lsb of the data until the cs inactive edge. timing diagrams iov dd /2 t o output pin i source (100a) i sink (100a) 25p f 13048-002 figure 2 . load circuit for timing characterization t 3 t 2 t 7 t 6 t 5 t 4 t 1 msb lsb dout/rd y (o) sclk (i) cs (i) i = inpu t , o = output 13048-003 figure 3 . read cycle ti ming diagram ( cs _en b it c leared) ad7124- 8 data sheet rev. b | page 12 of 91 t 5 t 3 t 2 t 4 t 1 msb dout/rd y (o) sclk (i) cs (i) i = inpu t , o = output lsb t 7a t 6 13048-004 figure 4. read cycle timing diagram ( cs _en b it s et) cs (i) sclk (i) din (i) msb lsb t 8 t 9 t 10 t 1 1 i = inpu t , o = output 13048-005 figure 5 . write cycle timing diagram write din dout/rd y sclk write t 12 t 12 t 12 read read 13048-006 figure 6. delay b etween consecutive serial operations din dout/rd y cs sclk t 13 13048-007 figure 7 . dout/ rdy h igh t ime when dout/ rdy is i nitially l ow and the n ext c onversion is a vailable sync (i) mclk (i) t 14 13048-008 figure 8. sync p ulse w idth data sheet ad7124- 8 rev. b | page 13 of 91 absolute maximum rat ings t a = 25c, unless otherwise noted. table 4 . parameter rating av dd to av ss ?0.3 v to +3.96 v io v dd to dgnd ?0.3 v to +3.96 v iov dd to dgnd ?0.3 v to +3.96 v iov dd to av ss ? 0.3 v to +5.94 v av ss to dgnd ? 1.98 v to + 0.3 v analog input voltage to av ss ?0.3 v to av dd + 0.3 v reference input voltage to av ss ?0.3 v to av d d + 0.3 v digital input voltage to dgnd ?0.3 v to iov dd + 0.3 v digital output voltage to dgnd ?0.3 v to iov dd + 0.3 v ain x / digital input current 10 ma operating temperature range ?40c to +1 0 5c storage temperature range ?65c to +150c ma ximum junction temperature 150c lead temperature, soldering reflow 260c esd ratings human body model ( hbm ) 4 kv f ield -i nduced c harged d evice m odel ( ficdm ) 1250 v machine model 400 v stresses at or above those listed under absolute maximum r atings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability . t hermal r esistance ja is specified for the worst case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 5 . thermal resistance package type ja jc unit 32- lead lfcsp 32.5 32.71 c/w esd caution ad7124- 8 data sheet rev. b | page 14 of 91 pin configuration an d function descripti ons notes 1. connect exposed p ad t o a v ss . cs regcapd ain5/iout/vbias/p4 iov dd dgnd ain0/iout/vbias ain1/iout/vbias ain2/iout/vbias/p1 ain3/iout/vbias/p2 ain4/iout/vbias/p3 regca p a a v ss refout ain15/iout/vbias/refin2(?) ain14/iout/vbias/refin2(+) ain13/iout/vbias ain12/iout/vbias ain 1 1/iout/vbias clk sclk din dout/rd y sync a v dd psw ain6/iout/vbias ain7/iout/vbias refin1(+) refin1(?) ain8/iout/vbias ain9/iout/vbias ain10/iout/vbias 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 32 31 30 29 28 27 26 25 ad7124-8 t o p view (not to scale) 13048-009 figure 9 . pin configuration table 6 . pin func tion descriptions pin no. mnemonic description 1 regcapd digital ldo regulator output. decouple this pin to dgnd with a 0.1 f capacitor. 2 iov dd serial interface supply voltage, 1.65 v to 3.6 v. iov dd is independent of av dd . therefore, the serial inter face can operate at 1.65 v with av dd at 3.6 v, for example. 3 dgnd digital ground reference point. 4 ain0/iout/vbias analog input 0/output of internal excitation current source/bias voltage. this input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. alternatively, the internal programmable excitation current source can be made available at this pin. either i out 1 or i out 0 can be switched to this output. a bias volt age midway between the analog power supply rails can be generated at this pin. 5 ain1/iout/vbias analog input 1/output of internal excitation current source/bias voltage. this input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. alternatively, the internal programmable excitation current source can be made available at this pin. either i out0 or i out1 can be switched to this output. a bias voltage midway between the analog power supply rails can be generated at this pin. 6 ain2/iout/vbias/p1 analog input 2/output of internal excitation current source/bias voltage/general - purpose output 1 . this input pin is configured via the configuration registers to be the positiv e or negative terminal of a differential or pseudo differential input. alternatively, the internal programmable excitation current source can be made available at this pin. either i out0 or i out1 can be switched to this output. a bias voltage midway between the analog power supply rails can be generated at this pin. th is pin can also be configured as a general - purpose output bit, referenced between av ss and av dd . 7 ain3/iout/vbias/p2 analog input 3/output of internal excitation current source/bias voltage/ general - purpose output 2 . this input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. alternatively, the internal programmable excitation current source can be made av ailable at this pin. either i out0 or i out1 can be switched to this output. a bias voltage midway between the analog power supply rails can be generated at this pin. th is pin can also be configured as a general - purpose output bit, referenced between av ss an d av dd . 8 ain4/iout/vbias/p3 analog input 4/output of internal excitation current source/bias voltage/general - purpose output 3 . this input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseu do differential input. alternatively, the internal programmable excitation current source can be made available at this pin. either i out0 or i out1 can be switched to this output. a bias voltage midway between the analog power supply rails can be generated at this pin. th is pin can also be configured as a general - purpose output bit, referenced between av ss and av dd . data sheet ad7124- 8 rev. b | page 15 of 91 pin no. mnemonic description 9 ain5/iout/vbias/p4 analog input 5/output of internal excitation current source/bias voltage/general - purpose output 4 . this input pin is conf igured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. alternatively, the internal programmable excitation current source can be made available at this pin. either i out0 or i out1 can b e switched to this output. a bias voltage midway between the analog power supply rails can be generated at this pin. th is pin can also be configured as a general - purpose output bit, referenced between av ss and av dd . 10 ain6 /iout/vbias analog input 6 /outp ut of internal excitation current source/bias voltage. this input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. alternatively, the internal programmable excitation current source can be made available at this pin. either i out0 or i out1 can be switched to this output. a bias voltage midway between the analog power supply rails can be generated at this pin. 11 ain7 /iout/vbias analog input 7 /output of internal excitat ion current source/bias voltage. this input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. alternatively, the internal programmable excitation current source can be made available at this pin. either i out0 or i out1 can be switched to this output. a bias voltage midway between the analog power supply rails can be generated at this pin. 12 refin1(+) positive reference input. an external reference can be applied betwe en refin1(+) and refin1(?). refin1(+) can be anywhere between av dd and av ss + 1 v . the nominal reference voltage (refin1(+) ? refin1(?)) is 2.5 v, but the device fu nctions with a reference from 1 v to av dd . 13 refin1(?) negative reference input. this re ference input can be anywhere between av ss and av dd ? 1 v. 1 4 ain 8 /iout/vbias analog input 8/output of internal excitat ion current source/bias voltage. this input pin is configured via the configuration registers to be the positive or negative terminal o f a differential or pseudo differential input. alternatively, the internal programmable excitation current source can be made available at this pin. either i out0 or i out1 can be switched to this output. a bias voltage midway between the analog power supply rails can be generated at this pin. 1 5 ain 9 /iout/vbias analog input 9/output of internal excitat ion current source/bias voltage. this input pin is configured via the configuration registers to be the positive or negative terminal of a differential or ps eudo differential input. alternatively, the internal programmable excitation current source can be made available at this pin. either i out0 or i out1 can be switched to this output. a bias voltage midway between the analog power supply rails can be generate d at this pin. 16 ain 10 /iout/vbias analog input 10/output of internal excitat ion current source/bias voltage. this input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential in put. alternatively, the internal programmable excitation current source can be made available at this pin. either i out0 or i out1 can be switched to this output. a bias voltage midway between the analog power supply rails can be generated at this pin. 1 7 ain 11 /iout/vbias analog input 11/output of internal excitat ion current source/bias voltage. this input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. alternatively, the internal programmable excitation current source can be made available at this pin. either i out0 or i out1 can be switched to this output. a bias voltage midway between the analog power supply rails can be generated at this pin. 1 8 ain 12 /iout/vbias ana log input 12/output of internal excitat ion current source/bias voltage. this input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. alternatively, the internal program mable excitation current source can be made available at this pin. either i out0 or i out1 can be switched to this output. a bias voltage midway between the analog power supply rails can be generated at this pin. 19 ain 13 /iout/vbias analog input 13/output of internal excitati on current source/bias voltage. this input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. alternatively, the internal programmable excitation cur rent source can be made available at this pin. either i out0 or i out1 can be switched to this output. a bias voltage midway between the analog power supply rails can be generated at this pin. 2 0 ain 14 /iout/vbias/ refin2(+) analog input 14 /output of intern al excitation current source/bias voltage/posi tive reference input. this input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. alternatively, the internal programmabl e excitation current source can be made av ailable at this pin. either i out0 or i out1 can be switched to this output. a bias voltage midway between the analog power supply rails can be generated at this pin. this pin also functions as a positive reference i nput for refin2 ( ) . refin2(+) can be anywhere between av dd and av ss + 1 v. the nominal reference voltage (refin2(+) to refin2(?)) is 2.5 v, but the device fu nctions with a reference from 1 v to av dd . ad7124- 8 data sheet rev. b | page 16 of 91 pin no. mnemonic description 2 1 ain 15 /iout/vbias/ refin2( ? ) analog input 15 /output of internal excita tion current source/bias voltage/ negative reference input. this input pin is configured via the configuration registers to be the positive or negative terminal of a differential or pseudo differential input. alternatively, the internal programmable excitation current source can be made available at this pin. either i out0 or i out1 can be switched to this output. a bias voltage midway between the analog power supply rails can be generated at this pin. this pin also functions as the negative reference input for refin2 ( ) . this reference input can be anywhere between av ss and av d d ? 1 v. 22 refout internal reference output. the buffered output of the internal 2.5 v voltage reference is available on this pin. 23 av ss analog supply voltage. the voltage on av dd is referenced to av ss . the differential between av dd and av ss must be between 2.7 v and 3.6 v in mid or low power mode and between 2.9 v and 3.6 v in full power mode . av ss can be taken below 0 v to provide a dual power supply to the ad7124 - 8 . for example, av ss c an be tied to ? 1.8 v and av dd can be tied to +1.8 v, providing a 1.8 v supply to the adc. 24 regcapa analog ldo regulator output. decouple this pin to av ss with a 0.1 f capacitor. 25 psw low - side power switch to av ss . 26 av dd analog supply voltage, r elative to a v ss . 27 sync synchronization input. this pin is a l ogic input that allows synchronization of the digital filters and analog modulators when using a number of ad7124 -8 d evices. wh en sync is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is held in a reset state. sync does not affect the digi tal interface but does reset rdy to a high state if it is low. 28 dout/ rdy serial data output/data ready output. dout/ rdy functions as a serial data output pin to access the output shift register of the adc. the output shift register can contain data from any of the on - chip data or c ontrol registers. in addition, dout/ rdy operates as a data ready pin, going low to indicate the completion of a conversion. if the data is not read after the conversion, the pin goes high before the next update occurs. the dout/ rdy falling edge can also be used as an interrupt to a processor, indicating that valid data is available. with an external serial clock, th e data can be read using the dout/ rdy pin. w hen cs is low, the data/control word information is placed on the dout/ rdy pin on the sclk falling edge and is valid on the sclk rising edge. 29 din serial data input to the input shift register on the adc. data in th e input shift register is transferred to the control registers within the adc , with the register selection bits of the communications register identifying the appropriate register. 30 sclk serial clock input. this serial clock input is for data transfers to and from the adc. the sclk p in has a schmitt - triggered input, making the interface suitable for opto - isolated applications. the serial clock can be continuous with all data tr ansmitted in a continuous train of pulses. alternatively, it can be a noncontinuous clock with the information being transmitted to or from the adc in smaller batches of data. 31 clk clock in put /clock out put . the internal clock can be made available at this pin. alternatively, the internal clock can be disabled, and the adc can be driven by an external clock. this allows several adcs to be driven from a common clock, allowing simultaneous conversions to be performed. 32 cs chip s elect input. this is an active low logic input that select s the adc. use cs to select the adc in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. cs can be hardwired low if the serial peripheral interface ( spi ) diagnostics are un u sed, allowing the adc to operate in 3 - wire mode with sclk, din, and dout interfac ing with the device. ep exposed pad. connect the exposed pad to a v ss . data sheet ad7124- 8 rev. b | page 17 of 91 t erm inology ain p ain p refers to the positive a nalog input. ain m ain m refers to the negative analog input . i ntegral n onlinearity (inl) inl is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. the end points of the transfer function are zero scale (not to be confused with bipolar zero), a point 0.5 lsb below the first code transition (000 000 to 000 001) , and full scale, a point 0.5 lsb above the last code transition (111 110 to 111 111). the er ror i s expressed in ppm of the full - s cale range. g ain e rror gain e rror is the deviation of the last code transition (111 110 to 111 111) from the ideal ain p voltage (ain m + v ref /gain ? 3/2 lsbs). gain error applies to both unipolar and bipolar analog i nput ranges. gain e rror is a measure of the span error of the adc. it includes full - scale errors but not zero - scale errors. for unipolar input ranges , it is defined as full - sca le error minus unipolar offset error; wh ereas for bipolar input ranges it i s def ined as full - scale error minus bipolar zero error . offset error offset e rror is the deviation of the first code transition from the ideal ain p voltage (ain m + 0.5 lsb) when operating in the unipolar mode. in bipolar mode, offset error is the deviation of t he midscale transition (0111 111 to 1000 000) from the ideal ain p voltage (ain m ? 0.5 lsb). o ffset c alibration r ange in t he system calibration modes, the ad7124 - 8 calibrates offset with re spect to the analog input. the o ffset c alibration r ange specification defines the range of voltages that the ad7124 - 8 can accept and still calibrate offset accurately. f ull -s cale c alibration r ange the f ull - scale calibration range is the range of voltages that the ad7124 - 8 can accept in the system calibration mode and still calibrate full scale correctly. i nput s pan in system calib ration schemes, two voltages applied in sequence to the ad7124 - 8 analog input define the analog input range. the input span specification defines the minimum and maximum input voltages from ze ro to full scale that the ad7124 - 8 can accept and still calibrate gain accurately. ad7124- 8 data sheet rev. b | page 18 of 91 typical performance characteristics 2500 0 500 1000 1500 2000 7fffce 7fffcf 7fffd0 7fffd1 7fffd2 7fffd3 7fffd4 7fffd5 7fffd6 7fffd7 7fffd8 7fffd9 7fffda 7fffdb 7fffdc occurrence codes (hex) 10,000 samples 13048-010 figure 10 . noise histogram plot (full p ower mode, post filter, output data rate = 25 sps , gain = 1) 1200 1000 800 600 400 200 0 7fffc6 7fffc7 7fffc8 7fffc9 7fffca 7fffcb 7fffcc 7fffcd 7fffce 7fffcf 7fffd0 7fffd1 7fffd2 7fffd3 7fffd4 7fffd5 7fffd6 7fffd7 7fffd8 7fffd9 7fffda 7fffdb 7fffdc 7fffde 7fffdd 7fffdf 7fffe0 7fffe1 7fffe2 7fffe3 occurrence codes (hex) 10,000 samples 13048-012 figure 11 . noise histogram plot (mid power mode, post filter, output data rate = 25 sps, gain = 1) 700 600 500 400 300 200 100 0 7fffc1 7fffc3 7fffc5 7fffc7 7fffc9 7fffcb 7fffcd 7fffcf 7fffd1 7fffd3 7fffd5 7fffd7 7fffd9 7fffdb 7fffdd 7fffdf 7fffe1 7fffe3 7fffe5 7fffe7 7fffe9 7fffeb 7fffed 7ffff0 7ffff2 occurrence codes (hex) 10,000 samples 13048-014 figure 12 . noise histogram plot (low p ower mode, post filter, output data rate = 25 sps, gain = 1) 350 300 250 200 150 100 50 0 7fffe9 7ffffa 800002 800009 800011 800019 800020 800028 800030 800038 80003f 800047 80004f 800057 80005e 800066 80006e 800075 80007d 800085 80008d 800094 80009c 8000a4 occurrence codes (hex) 10,000 samples 13048-0 1 1 figure 13 . noise histogram plot (full power mode, post filter, output data rate = 25 sps, gain = 128) 400 350 300 250 200 150 100 50 0 8388394.0 8388452.8 8388469.6 8388486.4 8388503.2 8388520.0 8388536.8 8388553.6 8388570.4 8388587.2 8388604.0 8388620.8 8388637.6 8388654.4 8388671.2 8388688.0 8388704.8 8388721.6 8388738.4 8388755.2 8388772.0 8388788.8 8388805.6 occurrence codes (hex) 10,000 samples 13048-013 figure 14 . noise histogram plot (mi d power mode, post filter, output data rate = 25 sps, gain = 128) 400 50 100 150 200 250 300 350 0 7ffeed 7fff03 7fff1a 7fff30 7fff47 7fff5d 7fff74 7fff8a 7fffa1 7fffb8 7fffce 7ffffb 7fffe5 800012 800028 80003f 800055 80006c 800083 800099 8000b0 8000c6 8000f3 80010a 800121 8000dd occurrence codes (hex) 10,000 samples 13048-015 figure 15 . noise histogram plot (low power mode, post filter, output data rate = 25 sps, gain = 128) data sheet ad7124- 8 rev. b | page 19 of 91 60 40 20 0 ?20 ?40 ?60 ?40 ?25 ?10 5 20 35 50 65 80 95 110 offset error (v) temperature (c) 28 units 13048-016 figure 16 . input referred offse t error vs. temperature (gain = 8, full power mode) 60 40 20 0 ?20 ?40 ?60 ?40 ?25 ?10 5 20 35 50 65 80 95 110 offset error (v) temperature (c) 28 units 13048-017 figure 17 . input referred offset error vs. temperature (gain = 8, mid power mode) 60 40 20 0 ?20 ?40 ?60 ?40 ?25 ?10 5 20 35 50 65 80 95 110 offset error (v) temperature (c) 28 units 13048-018 figure 18 . input referred offset error vs. temperature (gain = 8, low power mode) 60 40 20 0 ?20 ?40 ?60 ?40 ?25 ?10 5 20 35 50 65 80 95 110 offset error (v) temperature (c) 28 units 13048-019 figure 19 . input referred offset error vs. temperature (gain = 16, full power mode) 60 40 20 0 ?20 ?40 ?60 ?40 ?25 ?10 5 20 35 50 65 80 95 110 offset error (v) temperature (c) 28 units 13048-020 figure 20 . input referred offset error vs. temperature (gain = 16, mid power mode) 60 40 20 0 ?20 ?40 ?60 ?40 ?25 ?10 5 20 35 50 65 80 95 110 offset error (v) temperature (c) 28 units 13048-021 f igure 21 . input referred offset error vs. temperature (gain = 16, low power mode) ad7124- 8 data sheet rev. b | page 20 of 91 60 40 20 0 ?20 ?40 ?60 ?40 ?25 ?10 5 20 35 50 65 80 95 110 offset error (v) temperature (c) 29 units 13048-022 figure 22 . input referred offset error vs. temperature (gain = 1, analog input buffers enabled) 0.0010 0.0005 0 0.0005 0.0010 0.0015 ?40 ?25 ?10 5 20 35 50 65 80 95 110 gain error (%) temperature (c) 30 units 13048-023 figure 23 . input referred gain error vs. temperature (gain = 1) 0.015 0.010 0.005 0 ?0.005 ?0.010 ?40 ?25 ?10 5 20 35 50 65 80 95 110 gain error (%) temperature (c) 30 units 13048-024 figure 24 . input referred gain error vs. temperature (gain = 8) 0.045 0 0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 ?0.005 ?40 ?25 ?10 5 20 35 50 65 80 95 110 gain error (%) temperature (c) 30 units 13048-025 figure 25 . input referred gain error vs. temperature (gain = 1 6) ?2 ?1 0 1 2 3 ?3 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 inl (ppm of fsr) analog input voltage gain (v) gain = 1 gain = 8 gain = 16 13048-026 figure 26 . inl vs. differential input signal (analog input gain), odr = 50 sps , external 2.5 v reference ?4 ?3 ?2 ?1 0 1 2 3 4 ?2.5 ?1.5 ?0.5 0.5 1.5 2.5 in l (ppm of fsr) analog input vo lt age gain (v) gain = 1 gain = 8 gain = 16 13048-227 figure 27 . inl vs. differential input signal (analog input gain), odr = 50 sps , int ernal reference data sheet ad7124- 8 rev. b | page 21 of 91 25 20 15 10 5 0 2.498680 2.498879 2.499078 2.499277 2.499476 2.499675 2.499874 2.500073 2.500272 2.500471 2.500671 counts initial accuracy (v) 109 units 13048-027 figure 28 . internal reference voltage histogram 2.502 2.501 2.500 2.499 2.498 2.497 2.496 2.495 2.494 ?40 ?15 10 35 60 85 110 interna l reference vo lt age (v) temperature (c) 28 units 13048-028 figure 29 . internal reference voltage vs. temperature 25 20 15 10 5 0 ?4.262140 ?4.089392 ?3.916644 ?3.743986 ?3.571148 ?3.398400 ?3.225652 ?3.052904 ?3.880156 ?2.707408 ?2.534660 occurrence excitation current accuracy (%) 109 units 13048-030 figure 30 . ioutx current i nitial a ccuracy h istog ram (500 a) 25 20 30 15 10 5 0 ?1.01835 ?0.99035 ?0.96235 ?0.93435 ?0.90635 ?0.87835 ?0.85035 ?0.82235 ?0.79435 ?0.76635 ?0.85035 occurrence excitation current matching (%) 109 units 13048-031 figure 31 . ioutx current i nitial m atching h istogram (500 a) 490 465 470 475 480 485 460 ?40 ?25 ?10 5 35 20 50 65 80 95 110 excitation current (a) temperature (c) 29 units 13048-032 figure 32 . excitation current drift (500 a) 0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 ?1.2 ?40 ?25 ?10 5 35 20 50 65 80 95 110 excitation current mismatch (%) temperature (c) 29 units 13048-033 figure 33 . excitation current drift matching (50 0 a ) ad7124- 8 data sheet rev. b | page 22 of 91 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 0.33 0.66 0.99 1.65 1.32 1.98 2.31 2.64 2.97 3.30 excitation current (normalized) v load (v) 13048-034 50a 100a 250a 500a 750a 1ma figure 34 . output compliance ( av dd = 3.3 v) 1.000 0.950 0.955 0.960 0.965 0.970 0.975 0.980 0.985 0.990 0.995 0 0.33 0.66 0.99 1.65 1.32 1.98 2.31 2.64 2.97 3.30 excitation current (normalized) v load (v) 50a 100a 250a 500a 750a 13048-035 figure 35 . output compliance ( av dd = 3.3 v) 1200 1000 800 600 400 200 0 ?40 ?25 ?10 5 35 20 50 65 80 95 110 analog current (a) temperature (c) gain = 1, ain buffers off gain = 2 to 8 gain = 1, ain buffers on gain = 16 to 128 13048-036 figure 36 . analog current vs. temperature (full power mode) 450 400 350 300 250 200 150 100 50 0 ?40 ?25 ?10 5 35 20 50 65 80 95 110 analog current (a) temperature (c) gain = 1, ain buffers off gain = 2 to 8 gain = 1, ain buffers on gain = 16 to 128 13048-037 figure 37 . analog current vs. temperature (mid power mode) 300 250 200 150 100 50 0 ?40 ?25 ?10 5 35 20 50 65 80 95 110 analog current (a) temperature (c) gain = 1, ain buffers off gain = 2 to 8 gain = 1, ain buffers on gain = 16 to 128 13048-038 figure 38 . analog current vs. temperature (low power mode) 60 50 40 30 20 10 0 ?40 ?25 ?10 5 35 20 50 65 80 95 110 digital current (a) temperature (c) full power mid power low power 13048-039 figure 39 . digital current vs. temperature data sheet ad7124- 8 rev. b | page 23 of 91 6 4 2 0 ?14 ?12 ?10 ?8 ?6 ?4 ?2 ?40 ?20 0 20 40 60 80 100 current (na) temperature (c) gain = 1 gain = 4 gain = 16 gain = 64 gain = 2 gain = 8 gain = 32 gain = 128 13048-040 figure 40 . absolute analog input current vs. temperature (full power mode) 2 0 ?10 ?8 ?6 ?4 ?2 ?40 ?20 0 20 40 60 80 100 current (na) temperature (c) gain = 1 gain = 4 gain = 16 gain = 64 gain = 2 gain = 8 gain = 32 gain = 128 13048-042 figure 41 . absolute analog input current vs. temperature (mid power mode) 1 0 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 ?40 ?20 0 20 40 60 80 100 current (na) temperature (c) gain = 1 gain = 4 gain = 16 gain = 64 gain = 2 gain = 8 gain = 32 gain = 128 13048-044 figure 42 . absolute analog input c urrent vs. temperature (low power mode) 4 1 2 3 0 ?7 ?6 ?5 ?4 ?3 ?2 ?1 ?40 ?20 0 20 40 60 80 100 current (na) temperature (c) gain = 1 gain = 4 gain = 16 gain = 64 gain = 2 gain = 8 gain = 32 gain = 128 13048-041 figure 43 . differential analog input current vs. temperature (full power mode) 1 2 0 ?6 ?5 ?4 ?3 ?2 ?1 ?40 ?20 0 20 40 60 80 100 120 current (na) temperature (c) gain = 1 gain = 4 gain = 16 gain = 64 gain = 2 gain = 8 gain = 32 gain = 128 13048-043 figure 44 . differential analog input current vs. temperature (mid power mode) 1 0 ?6 ?5 ?4 ?3 ?2 ?1 ?40 ?20 0 20 40 60 80 100 current (na) temperature (c) gain = 1 gain = 4 gain = 16 gain = 64 gain = 2 gain = 8 gain = 32 gain = 128 13048-045 figure 45 . differential analog input current vs. temperature (low power mode) ad7124- 8 data sheet rev. b | page 24 of 91 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 ?3.5 ?4.0 ?40 ?20 0 40 20 60 80 100 current (na) temperature (c) full power mid power low power 13048-046 figure 46 . reference input current vs. temperature (reference buffers enabled) ?0.6 ?0.4 ?0.2 0.2 0.4 0.6 0.8 1.0 1.2 0 ?40 ?30 ?20 ?10 0 25 15 40 50 60 70 85 95 105 temperature sensor error (c) temperature (c) 32 units 13048-047 figure 47 . temperature sensor accuracy 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 10 100 1k 10k peak-to-peak resolution (bits) output data rate, settled (sps) g = 1 buff off g = 1 g = 2 g = 4 g = 8 g = 16 g = 32 g = 64 g = 128 13048-048 figure 48 . peak - to - peak resolution vs. output data rate (settled ), sinc 4 filter (full power mode) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 10 100 1k 10k peak-to-peak resolution (bits) output data rate, settled (sps) g = 1 buff off g = 1 g = 2 g = 4 g = 8 g = 16 g = 32 g = 64 g = 128 13048-049 figure 49 . peak - to - peak resolution vs. output data rate (settled ), si nc 3 filter (full power mode) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 10 100 1k 10k peak-to-peak resolution (bits) output data rate (sps) g = 1 buff off g = 1 g = 2 g = 4 g = 8 g = 16 g = 32 g = 64 g = 128 13048-050 figure 50 . peak - to - peak resolution vs. output data rat e, sinc 4 + sinc 1 filter (full power mode ) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 10 100 1k 10k peak-to-peak resolution (bits) output data rate (sps) g = 1 buff off g = 1 g = 2 g = 4 g = 8 g = 16 g = 32 g = 64 g = 128 13048-051 figure 51 . peak - to - peak resolution vs. output data rate , sinc 3 + sinc 1 fi lter (full power mode ) data sheet ad7124- 8 rev. b | page 25 of 91 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 10 100 1k 100k 10k peak-to-peak resolution (bits) output data rate, settled (sps) g = 1 buff off g = 1 g = 2 g = 4 g = 8 g = 16 g = 32 g = 64 g = 128 13048-052 figure 52 . peak - to - peak resolution vs. output data rate (settled ), sinc 4 filter (mid power mode) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 10 100 1k 100k 10k peak-to-peak resolution (bits) output data rate, settled (sps) g = 1 buff off g = 1 g = 2 g = 4 g = 8 g = 16 g = 32 g = 64 g = 128 13048-053 figure 53 . peak - to - peak resolution vs. output data rate (settled ), sinc 3 filte r (mid power mode) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 10 100 1k peak-to-peak resolution (bits) output data rate (sps) g = 1 buff off g = 1 g = 2 g = 4 g = 8 g = 16 g = 32 g = 64 g = 128 13048-054 figure 54 . peak - to - peak resolution vs. output data rate , sinc 4 + sinc 1 filter (mid power mode) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 10 100 1k peak-to-peak resolution (bits) output data rate (sps) g = 1 buff off g = 1 g = 2 g = 4 g = 8 g = 16 g = 32 g = 64 g = 128 13048-055 figure 55 . peak - to - peak resolution vs. output data rate , sinc 3 + sinc 1 filter (mid p ower mode) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 10 100 1k 10k peak-to-peak resolution (bits) output data rate, settled (sps) g = 1 ain buff off g = 1 g = 2 g = 4 g = 8 g = 16 g = 32 g = 64 g = 128 13048-056 figure 56 . peak - to - peak resolution vs. output data rate (settled ), sinc 4 filter (low power mode) 23 22 21 20 19 18 17 16 15 14 13 12 11 9 10 1 10 100 1k 10k peak-to-peak resolution (bits) output data rate, settled (sps) g = 1 ain buff off g = 1 g = 2 g = 4 g = 8 g = 16 g = 32 g = 64 g = 128 13048-057 figure 57 . peak - to - peak resolution vs. output data rate (settled ), sinc 3 filter (low power mode) ad7124- 8 data sheet rev. b | page 26 of 91 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 10 100 1k peak-to-peak resolution (bits) output data rate (sps) g = 1 buff off g = 1 g = 2 g = 4 g = 8 g = 16 g = 32 g = 64 g = 128 13048-058 figure 58 . peak - to - peak resolution vs. output data rate , sinc 4 + sinc 1 filter (low power mode ) 23 22 21 20 19 18 17 16 15 14 13 12 11 10 1 10 100 1k peak-to-peak resolution (bits) output data rate (sps) g = 1 buff off g = 1 g = 2 g = 4 g = 8 g = 16 g = 32 g = 64 g = 128 13048-059 figure 59 . peak - to - peak resolution vs. output data rate , sinc 3 + sinc 1 filter (low power mode) 0 50 100 150 200 250 300 350 400 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 w ait time in s t andb y mode (seconds) analog current (a) gain = 1, low power gain = 8, low power gain = 16, low power gain = 1, mid power gain = 8, mid power gain = 16, mid power gain = 1, ful l power gain = 8, ful l power gain = 16, ful l power 13048-200 figure 60 . analog current vs . wait t ime in s tandby m ode , adc in s ingle c onversion m ode (50 sps ) 0 5 10 15 20 25 30 35 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 digi t a l current (a) w ait time in s t andb y mode (seconds) gain = 1, low power gain = 8, low power gain = 16, low power gain = 1, mid power gain = 8, mid power gain = 16, mid power gain = 1, ful l power gain = 8, ful l power gain = 16, ful l power 13048-201 figure 61 . digital current vs . wait t ime in s tandby m ode , adc in s ingle c onversion m ode (50 sps ) 0 200 400 600 800 1000 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 rms noise (nv) analog input vo lt age (v) low power, externa l ref mid power, externa l ref ful l power, externa l ref low power interna l ref mid power, interna l ref ful l power, interna l ref 13048-202 fi gure 62 . rms noise vs . analog input voltage for the i nternal r eference and e xternal r eference (gain = 32, 50 sps ) 4 3 2 1 0 ?1 ?2 ?3 ?40 ?25 ?10 5 35 20 50 65 80 95 110 oscillator error (%) temperature (c) 29 units 13048-029 figure 63 . internal oscillator error vs. temperature data sheet ad7124- 8 rev. b | page 27 of 91 rms n o ise and r esolution table 7 through table 36 show the rms noise, peak - to - peak noise, effective resolution, and n oise - free (peak - to - peak) resolution of the ad7124 - 8 for various output data rates, gain settings , and filters. the numbers given are for the bipolar input range with an external 2.5 v reference. these nu mbers are typical and are generated with a differential input voltage of 0 v when the adc is continuous ly converting on a single channel. it is important to note that the effective resolution is calculated using the rms n oise, whereas the peak - to - peak resolution (shown in parentheses) is calculated based on peak - to - peak noise (shown in parentheses ) . the pea k - to - peak resolution represents the resolution for which there is no code flicker. effective r esolution = log 2 (input range/rms noise) peak - to - peak resolution = log 2 (input range/p eak - to - p eak noise full power mode sinc 4 table 7 . rm s noise ( peak -to - peak noise ) vs. gain and output data rate ( v) , full power mode filter word (dec.) output data rate ( sps ) output data rate (zero latency mode) ( sps ) f 3db (hz) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 2 047 9.4 2.34 2.16 0.24 (1.5) 0.15 (0.89) 0.091 (0.6) 0.071 (0.41) 0.045 (0.26) 0.031 (0.17) 0.025 (0.15) 0.023 (0.14) 1920 10 2.5 2.3 0.23 (1.5) 0.14 (0.89) 0.094 (0.6) 0.076 (0.42) 0.048 (0.27) 0.03 (0.19) 0.025 (0.16) 0.025 (0.15) 960 20 5 4.6 0.31 (2 .1) 0.22 (1.3) 0.13 (0.89) 0.1 (0.6) 0.069 (0.41) 0.044 (0.26) 0.035 (0.22) 0.034 (0.22) 480 40 10 9.2 0.42 (3) 0.3 (2.1) 0.19 (1.4) 0.14 (0.97) 0.09 (0.63) 0.063 (0.39) 0.053 (0.34) 0.043 (0.27) 384 50 12.5 11.5 0.48 (3.2) 0.33 (2.1) 0.2 (1.3) 0.16 (1.1 ) 0.1 (0.75) 0.068 (0.43) 0.059 (0.42) 0.048 (0.28) 320 60 15 13.8 0.51 (3.3) 0.35 (2.4) 0.23 (1.3) 0.17 (1.2) 0.11 (0.78) 0.077 (0.5) 0.064 (0.41) 0.056 (0.35) 240 80 20 18.4 0.6 (4.8) 0.41 (3) 0.28 (1.8) 0.19 (1.3) 0.13 (0.86) 0.09 (0.54) 0.072 (0.48) 0.063 (0.45) 120 160 40 36.8 0.86 (6.9) 0.55 (4.1) 0.37 (2.5) 0.29 (2) 0.2 (1.2) 0.13 (0.84) 0.11 (0.7) 0.098 (0.6) 60 320 80 73.6 1.2 (8.9) 0.76 (6.1) 0.53 (4.1) 0.4 (2.7) 0.26 (1.8) 0.18 (1.2) 0.15 (0.95) 0.14 (0.86) 30 640 160 147.2 1.7 (13) 1.1 (8.8 ) 0.74 (5.7) 0.57 (4.1) 0.38 (2.9) 0.26 (2) 0.22 (1.6) 0.19 (1.4) 15 1280 320 294.4 2.4 (19) 1.6 (13) 1.1 (8.4) 0.82 (6) 0.55 (4) 0.38 (2.5) 0.3 (2.3) 0.26 (1.8) 8 2400 600 552 3.3 (25) 2.3 (16) 1.5 (12) 1.2 (8) 0.76 (6) 0.53 (4) 0.43 (3.2) 0.37 (2.7) 4 4800 1200 1104 4.9 (38) 3.4 (25) 2.4 (20) 2 (13) 1.3 (9.1) 0.83 (6.4) 0.68 (4.8) 0.58 (4.3) 2 9600 2400 2208 8.8 (76) 6.8 (61) 4.9 (34) 4.3 (27) 2.6 (21) 1.7 (13) 1.3 (12) 1.2 (9.4) 1 19 , 200 4800 4416 72 (500) 38 (270) 21 (150) 13 (95) 7.5 (57) 4.4 (33) 3.3 (26) 2.8 (23) table 8 . effective resolution ( peak -to - peak resolution ) vs. gai n and output data rate (bits) , full power mode filter word (dec.) output data rate ( sps ) output data rate (zero latency mode) ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 2047 9.4 2.34 24 (21.7) 24 (21.4) 23.7 (21) 23.1 (20.5) 22.7 (20.2) 22.3 (19.8) 21.6 (19) 20.7 (18.1) 1920 10 2.5 24 (21.7) 24 (21.4) 23.7 (21) 23 (20.5) 22.6 (20.1) 22.3 (19.7) 21.6 (19) 20.7 (18.1) 960 20 5 23.9 (21.2) 23.5 (20.8) 23.2 (20.4) 22.5 (20) 22.1 (19.5) 21.8 (19.2) 21.1 (18.4) 20.1 (19.4) 480 40 10 23.5 (20.7) 23 (20.3) 22.6 (19.8) 22.1 (19.3) 21.7 (18.9) 21.2 (18.6) 20.5 (17.8) 19.8 (17.1) 384 50 12.5 23.3 (20.5) 22.9 (20.2) 22. 5 (19.6) 21.9 (19.1) 21.5 (18.7) 21.1 (18.5) 20.4 (17.7) 19.6 (17) 320 60 15 23.2 (20.3) 22.8 (20) 22.4 (19.5) 21.8 (19) 21.4 (18.6) 21 (18.3) 20.2 (17.6) 19.4 (16.6) 240 80 20 23 (20) 22.6 (19.7) 22.1 (19.3) 21.6 (18.9) 21.2 (18.5) 20.7 (18.1) 20 (17.3) 19.2 (16.4) 120 160 40 22.5 (19.5) 22.1 (19.2) 21.7 (18.9) 21 (18.3) 20.6 (18) 20.1 (17.5) 19.5 (16.9) 18.6 (16) 60 320 80 22 (19.1) 21.6 (18.6) 21.2 (18.2) 20.6 (17.8) 20.2 (17.4) 19.7 (17) 19 (16.3) 18.1 (15.5) 30 640 160 21.5 (18.5) 21.1 (18.1) 20.7 (17.7) 20.1 (17.2) 19.7 (16.8) 19.2 (16.3) 18.5 (15.6) 17.6 (14.8) 15 1280 320 21 (18) 20.5 (17.6) 20.2 (17.2) 19.5 (16.7) 19.1 (16.3) 18.7 (15.9) 18 (15.1) 17.2 (14.4) 8 2400 600 20.5 (17.5) 20.1 (17.2) 19.7 (16.7) 19 (16.2) 18.6 (15.7) 18.2 (15.3) 17 .5 (14.6) 16.7 (13.8) 4 4800 1200 20 (17) 19.5 (16.5) 19 (16) 18.3 (15.6) 17.9 (15.1) 17.5 (14.6) 16.8 (14) 16 (13.2) 2 9600 2400 19.1 (16) 18.5 (15.3) 18 (15.1) 17.2 (14.5) 16.9 (13.9) 16.5 (13.5) 15.9 (12.7) 15 (12) 1 19 , 200 4800 16.1 (13.3) 16 (13.2) 15.9 (13) 15.5 (12.7) 15.4 (12.4) 15.1 (12.2) 14.6 (11.5) 13.8 (10.8) ad7124- 8 data sheet rev. b | page 28 of 91 sinc 3 table 9 . rms noise (peak -to - peak noise ) vs. gain and output data rate ( v) , full power mode filter word (dec.) output data rate ( sps ) o utput data rate (z ero latency mode) ( sps ) f 3db (hz) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 2047 9.4 3.13 2.56 0.37 (1.5) 0.15 (0.89) 0.096 (0.58) 0.07 (0.38) 0.046 (0.25) 0.033 (0.16) 0.023 (0.11) 0.017 (0.09) 1920 10 3.33 2.72 0.24 ( 1.5) 0.15 (0.89) 0.096 (0.6) 0.07 (0.4) 0.05 (0.26) 0.034 (0.17) 0.023 (0.12) 0.018 (0.09) 1280 20 5 5.44 0.31 (1.8) 0.18 (1.2) 0.12 (0.82) 0.09 (0.55) 0.059 (0.35) 0.041 (0.24) 0.033 (0.18) 0.027 (0.14) 640 30 10 8.16 0.4 (2.6) 0.26 (1.6) 0.17 (1.2) 0.1 1 (0.82) 0.088 (0.52) 0.055 (0.36) 0.048 (0.27) 0.039 (0.22) 384 50 16.67 13.6 0.53 (3.3) 0.3 (2.2) 0.2 (1.6) 0.17 (1.1) 0.1 (0.75) 0.075 (0.51) 0.062 (0.39) 0.056 (0.33) 320 60 20 16.32 0.55 (3.6) 0.37 (2.4) 0.24 (1.8) 0.19 (1.3) 0.12 (0.8) 0.084 (0.54) 0.068 (0.44) 0.06 (0.37) 160 120 40 32.64 0.78 (5.1) 0.53 (3.4) 0.35 (2.3) 0.26 (1.8) 0.17 (1.1) 0.12 (0.85) 0.1 (0.66) 0.097 (0.55) 80 240 80 65.28 1.1 (7) 0.73 (4.9) 0.49 (3.2) 0.37 (2.6) 0.25 (1.6) 0.17 (1.2) 0.14 (1) 0.12 (0.78) 40 480 160 130.56 1 .5 (11) 1.1 (6.8) 0.67 (4.5) 0.52 (3.7) 0.34 (2.2) 0.25 (1.7) 0.19 (1.4) 0.17 (1.2) 20 960 320 261.12 2.3 (16) 1.5 (9.8) 0.99 (6.6) 0.75 (5.1) 0.53 (3.5) 0.35 (2.4) 0.28 (2.1) 0.25 (1.8) 10 1920 640 522.24 3.2 (26) 2.2 (16) 1.5 (11) 1.1 (8.5) 0.73 (5.5) 0.49 (3.9) 0.4 (3.2) 0.35 (2.7) 6 3200 1066.67 870.4 4.9 (38) 3.2 (24) 2.1 (15) 1.6 (12) 1 (7.7) 0.68 (5.6) 0.56 (4.2) 0.48 (3.6) 3 6400 2133.33 1740.8 25 (170) 13 (89) 7.1 (54) 4.3 (35) 2.4 (18) 1.5 (11) 1.1 (8.4) 0.9 (6.7) 2 9600 3200 2611.2 110 (820) 54 (390) 28 (210) 14 (110) 7.4 (57) 3.9 (27) 2.3 (17) 1.7 (13) 1 19 , 200 6400 5222.4 890 (6 500) 430 (3 000) 220 (1 500) 110 (790) 55 (390) 28 (190) 14 (100) 7.6 (56) table 10 . effective resolution (peak-to - peak resolution) vs. gain and output d a ta rate , full power mode filter word (dec.) output data rate ( sps ) output data rate (zero l atency mode) ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 2047 9.4 3.13 24 (21.7) 24 (21.4) 23.6 (21) 23.1 (20.6 ) 22.7 (20.3) 22.2 (19.9) 21.7 (19.3) 21 (18.7) 1920 10 3.33 24 (21.7) 24 (21.4) 23.6 (21) 23.1 (20.6) 22.6 (20.2) 22.2 (19.8) 21.7 (19.3) 21 (18.7) 1280 20 5 24 (21.4) 23.7 (21) 23.2 (20.5) 22.7 (20.1) 22.3 (19.8) 21.9 (19.3) 21.2 (18.7) 20.5 (18.1) 64 0 30 10 23.6 (20.9) 23.2 (20.5) 22.8 (20) 22.2 (19.5) 21.8 (19.2) 21.4 (18.7) 20.6 (18.1) 19.9 (17.4) 384 50 16.67 23.2 (20.5) 22.8 (20.1) 22.4 (19.6) 21.8 (19.1) 21.4 (18.7) 21 (18.2) 20.3 (17.6) 19.4 (16.9) 320 60 20 23.1 (20.4) 22.7 (20) 22.3 (19.4) 2 1.7 (18.9) 21.3 (18.6) 20.8 (18.1) 20.1 (17.4) 19.3 (16.7) 160 120 40 22.6 (19.9) 22.2 (19.5) 21.8 (19) 21.2 (18.4) 20.8 (18.1) 20.3 (17.5) 19.6 (26.9) 18.7 (16.1) 80 240 80 22.1 (19.4) 21.7 (19) 21.3 (18.6) 20.7 (17.9) 20.3 (17.6) 19.8 (17) 19.1 (16.3) 18.3 (15.6) 40 480 160 21.6 (18.8) 21.2 (18.5) 20.8 (18.1) 20.2 (17.4) 19.8 (17.1) 19.3 (16.5) 18.6 (15.8) 17.8 (15) 20 960 320 21.1 (18.3) 20.7 (18) 20.3 (17.5) 19.7 (16.9) 19.2 (16.4) 18.8 (16) 18.1 (15.2) 17.3 (14.4) 10 1920 640 20.6 (17.6) 20.1 (17. 2) 19.7 (16.8) 19.1 (16.2) 18.7 (15.8) 18.3 (15.3) 17.6 (14.6) 16.8 (13.8) 6 3200 1066.67 19.9 (17) 19.6 (16.6) 19.2 (16.3) 18.6 (15.6) 18.2 (15.3) 17.8 (14.8) 17.1 (14.2) 16.3 (13.4) 3 6400 2133.33 17.6 (14.8) 17.6 (14.8) 17.4 (14.5) 17.2 (14.1) 17 (14. 1) 16.7 (13.8) 16.3 (13.2) 15.4 (12.5) 2 9600 3200 15.5 (12.6) 15.5 (12.6) 15.4 (12.6) 15.4 (12.5) 15.4 (12.4) 15.3 (12.5) 15 (12.2) 14.5 (11.6) 1 19 , 200 6400 12.5 (9.7) 12.5 (9.7) 12.5 (9.7) 12.5 (9.6) 12.5 (9.6) 12.4 (9.6 12.4 (9.6) 12.3 (9.5) post filters table 11 . rms noise (peak -to - peak noise) vs. gain and output data rate (v), full power mode output data rate ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 16.67 0.51 (3.3) 0.34 (2.1) 0 .21 (1.3) 0.16 (0.97) 0.11 (0.65) 0.075 (0.41) 0.062 (0.34) 0.051(0.3) 20 0.53 (3.3) 0.36 (2.1) 0.23 (1.3) 0.18 (1) 0.11 (0.65) 0.078 (0.45) 0.062 (0.34) 0.051 (0.3) 25 0.57 (3.6) 0.37 (2.2) 0.25 (1.6) 0.18 (1.2) 0.12 (0.75) 0.082 (0.47) 0.062 (0.38) 0.0 55 (0.31) 27.27 0.6 (3.9) 0.38 (2.2) 0.26 (1.6) 0.19 (1.2) 0.13 (0.82) 0.084 (0.55) 0.072 (0.44) 0.063 (0.43) data sheet ad7124- 8 rev. b | page 29 of 91 table 12 . effective resolution (peak-to - peak resolution) vs. gain and output data rate (bits), full power mode output data rate ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 16.67 23.2 (20.5) 22.8 (20.2) 22.5 (19.9) 21.9 (19.3) 21.5 (18.9) 21 (18.5) 20.3 (17.8) 19.5 (17) 20 23.2 (20.5) 22.7 (20.2) 22.3 (19.9) 21.7 (19.2) 21.5 (18.9) 20.9 (18.4) 20.3 (17.8) 19.5 (17) 25 23.1 (20.4) 22.7 (20.1) 22.2 (19.6) 21.7 (19) 21.3 (18.7) 20.9 (18.3) 20.3 (17.7) 19.5 (17) 27.27 23 (20.3) 22.6 (20.1) 22.2 (19.5) 21.7 (19) 21.2 (18.5) 20.8 (18.1) 20.1 (17.4) 19.2 (16.5) fast settling filter ( si nc 4 + sinc 1 ) table 13 . rms noise (peak -to - peak noise) vs. gain and output data rate (v) , full power mode (average by 16) filter word (dec.) output data rate ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 ga in = 128 384 2.63 0.19 (1.2) 0.11 (0.75) 0.077 (0.52) 0.063 (0.34) 0.036 (0.21) 0.027 (0.17) 0.021 (0.11) 0.019 (0.098) 120 8.42 0.32 (2.1) 0.2 (1.3) 0.13 (0.97) 0.1 (0.63) 0.067 (0.46) 0.045 (0.28) 0.039 (0.23) 0.031 (0.2) 24 42.11 0.69 (4.6) 0.44 (3) 0.29 (2.1) 0.23 (1.6) 0.14 (0.99) 0.1 (0.72) 0.081 (0.54) 0.07 (0.49) 20 50.53 0.71 (5.1) 0.49 (3.1) 0.3 (2.2) 0.25 (1.7) 0.16 (1.1) 0.11 (0.78) 0.09 (0.6) 0.082 (0.57) 2 505.26 2.4 (18) 1.6 (10) 1.1 (8.3) 0.87 (5.5) 0.56 (3.5) 0.47 (2.9) 0.33 (2.1) 0.3 (2) 1 1010.53 4.8 (35) 3 (20) 1.9 (12) 1.4 (8.8) 0.89 (5.2) 0.57 (3.7) 0.49 (3) 0.44 (3) table 14. effective resolution ( peak -to - peak resolution ) vs. gai n and output data rate (bits) , full power mode (average by 16) filter word ( dec.) output data rate ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 384 2.63 24 (22) 24 (21.7) 23.9 (21.2) 23.3 (20.8) 23 (20.5) 22.5 (19.8) 21.8 (19.5) 21 (18.6) 120 8.42 23.9 (21.2) 23.6 (20.8) 23.3 (20.3) 22.5 (19 .9) 22.2 (19.4) 21.9 (19.1) 20.9 (18.4) 20.2 (17.6) 24 42.11 22.8 (20) 22.4 (19.7) 22.1 (19.2) 21.4 (18.6) 21.1 (18.3) 20.5 (17.7) 19.9 (17.1) 19.1 (16.3) 20 50.53 22.7 (19.9) 22.3 (19.6) 22 (19.1) 21.2 (18.5) 20.9 (18.1) 20.4 (17.6) 19.7 (17) 18.9 (16. 1) 2 505.26 21 (18.1) 20.6 (17.9) 20.2 (17.2) 19.5 (16.8) 19.1 (16.4) 18.4 (15.7) 17.8 (15.2) 17 (14.3) 1 1010.53 20 (17.1) 19.7 (16.9) 19.3 (16.6) 18.8 (16.1) 18.4 (15.9) 18.1 (15.4) 17.3 (14.7) 16.5 (13.7) fast settling filter ( sinc 3 + sinc 1 ) table 15 . rms noise (peak -to - peak noise) vs. gain and output data rate (v) , full power mode (average by 16) filter word (dec.) output data rate ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 384 2.78 0 .22 (1.4) 0.13 (0.75) 0.081 (0.44) 0.048 (0.3) 0.039 (0.24) 0.026 (0.18) 0.025 (0.13) 0.019 (0.11) 120 8.89 0.31 (2.1) 0.21 (1.3) 0.13 (0.89) 0.1 (0.63) 0.068 (0.47) 0.047 (0.28) 0.036 (0.25) 0.033 (0.17) 24 44.44 0.7 (4.8) 0.46 (3.1) 0.29 (2.1) 0.22 (1. 5) 0.14 (0.95) 0.098 (0.67) 0.079 (0.56) 0.071 (0.44) 20 53.33 0.77 (5.2) 0.5 (3.4) 0.31 (2.3) 0.24 (1.6) 0.17 (1) 0.11 (0.73) 0.09 (0.66) 0.077 (0.48) 2 533.33 6.1 (46) 3.2 (23) 1.8 (12) 1.1 (7.5) 0.65 (4.3) 0.4 (2.7) 0.31 (2.2) 0.27 (2) 1 1066.67 44 ( 320) 22 (160) 11 (80) 5.7 (40) 2.9 (22) 1.5 (11) 0.83 (6.2) 0.54 (4) table 16. effective resolution ( peak -to - peak resolution ) vs. gai n and output data rate (bits) , full power mode (average by 16) filter word (dec.) output data rat e ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 384 2.78 24 (21.8) 24 (21.7) 23.9 (21.4) 23.6 (21) 22.9 (20.3) 22.5 (19.8) 21.6 (19.2) 21 (18.4) 120 8.89 24 (21.2) 23.5 (20.9) 23.2 (20.4) 22.6 (19.9) 22.1 (19.4) 21.7 (19.1) 21 (18.3) 20.2 (17.8) 24 44.44 22.8 (20) 22.4 (19.6) 22.1 (19.2) 21.4 (18.7) 21.1 (18.3) 20.6 (17.8) 19.9 (17.1) 19.1 (16.5) 20 53.33 22.6 (19.9) 22.3 (19.5) 22 (19.1) 21.3 (18.6) 20.8 (18.2) 20.4 (17.7) 19.7 (16.9) 19 (16.3) 2 533.33 19.7 (16.8 ) 19.6 (16.8) 19.4 (16.6) 19.1 (16.3) 18.9 (16.1) 18.6 (15.8) 17.9 (15.1) 17.2 (14.3) 1 1066.67 16.8 (13.9) 16.8 (13.9) 16.8 (13.9) 16.7 (13.9) 16.7 (13.8) 16.6 (13.8) 16.5 (13.6) 16.1 (13.3) ad7124- 8 data sheet rev. b | page 30 of 91 mid power mode sinc 4 table 17 . rms no ise ( peak -to - peak noise) vs. gain and output data rate ( v ) , mid power mode filter word (dec.) output data rate ( sps ) output data rate (zero latency mode) ( sps ) f 3db (hz) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 2047 2. 34 0.586 0.078 0.22 (1.4) 0.14 (0.88) 0.095 (0.6) 0.062 (0.38) 0.048 (0.24) 0.036 (0.17) 0.024 (0.14) 0.02 (0.1) 1920 2.5 0.625 0.575 0.25 (1.4) 0.17 (0.88) 0.11 (0.6) 0.073 (0.38) 0.048 (0.24) 0.037 (0.19) 0.024 (0.14) 0.021 (0.1) 960 5 1.25 1.15 0.34 (2) 0.21 (1.2) 0.13 (0.77) 0.085 (0.52) 0.064 (0.36) 0.052(0.25) 0.04 (0.21) 0.035 (0.2) 480 10 2.5 2.3 0.44 (2.8) 0.28 (1.8) 0.19 (1.1) 0.1 (0.82) 0.1 (0.55) 0.072 (0.41) 0.057 (0.34) 0.048 (0.28) 240 20 5 4.6 0.67 (3.8) 0.4 (2.4) 0.27 (1.6) 0.2 (1.1) 0 .14 (0.85) 0.098 (0.64) 0.081 (0.47) 0.07 (0.43) 120 40 10 9.2 0.98 (6) 0.58 (3.6) 0.37 (2.3) 0.27 (1.7) 0.2 (1.1) 0.14 (0.87) 0.11 (0.74) 0.09 (0.57) 96 50 12.5 11.5 1 (7.4) 0.67 (4.2) 0.41 (2.5) 0.28 (1.9) 0.23 (1.3) 0.15 (0.95) 0.13 (0.78) 0.11 (0.7) 80 60 15 13.8 1.1 (7.2) 0.7 (4.3) 0.44 (3) 0.33 (2.1) 0.24 (1.4) 0.17 (1.1) 0.14 (0.89) 0.12 (0.75) 60 80 20 18.4 1.3 (8.4) 0.8 (5.1) 0.53 (3.4) 0.37 (2.4) 0.27 (1.6) 0.2 (1.3) 0.18 (1.1) 0.13 (0.82) 30 160 40 36.8 1.8 (11) 1.2 (7.6) 0.73 (4.6) 0.54 (3. 4) 0.39 (2.4) 0.28 (1.9) 0.23 (1.4) 0.19 (1.2) 15 320 80 73.6 2.6 (17) 1.7 (11) 1 (6.6) 0.79 (4.7) 0.58 (3.4) 0.4 (2.5) 0.33 (2) 0.26 (1.5) 8 600 150 138 3.7 (23) 2.3 (15) 1.5 (9.6) 1.2 (7.2) 0.84 (5) 0.56 (4) 0.46 (2.8) 0.4 (2.6) 4 1200 300 276 5.3 (36 ) 3.6 (24) 2.4 (16) 1.9 (13) 1.3 (8.2) 0.85 (6) 0.68 (4.3) 0.6 (4.5) 2 2400 600 552 9.3 (72) 6.8 (53) 4.8 (35) 4.1 (34) 2.5 (19) 1.7 (13) 1.3 (10) 1.2 (9.7) 1 4800 1200 1104 71 (500) 37 (270) 21 (160) 13 (98) 7.2 (55) 4.3 (33) 3.1 (24) 2.6 (21) table 18 . effective resolution (peak-to - peak resolution) vs. gain and output data rate (bits) , mid power mode filter word (dec.) output data rate ( sps ) output data rate (zero latency mode) ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 2047 2.34 0.586 24 (21.8) 24 (21.4) 23.6 (21) 23.3 (20.6) 22.6 (20.3) 22.1 (19.7) 21.6 (19.1) 20.9 (18.5) 1920 2.5 0.625 24 (21.8) 23.8 (21.4) 23.5 (21) 23 (20.6) 22.6 (20.3) 22 (19.7) 21.6 (19.1) 20.8 (18.5) 960 5 1.25 2 3.8 (21.2) 23.5 (21) 23.2 (20.6) 22.8 (20.2) 22.2 (19.7) 21.5 (19.2) 20.9 (18.5) 20.1 (17.6) 480 10 2.5 23.4 (20.8) 23.1 (20.4) 22.7 (20.1) 22.2 (19.6) 21.5 (19.1) 21 (18.5) 20.4 (17.8) 19.6 (17.1) 240 20 5 22.8 (20.3) 22.5 (20) 22.1 (19.6) 21.6 (19.1) 2 1.1 (18.5) 20.6 (17.9) 19.9 (17.3) 19.1 (16.5) 120 40 10 22.3 (19.7) 22 (19.4) 21.7 (19) 21.1 (18.5) 20.6 (18.1) 20.1 (17.5) 19.4 (16.8) 18.7 (16) 96 50 12.5 22.2 (19.5) 21.8 (19.2) 21.5 (18.9) 21 (18.3) 20.4 (17.9) 19.9 (17.3) 19.2 (16.6) 18.5 (15.8) 8 0 60 15 22.1 (19.4) 21.7 (19.1) 21.4 (18.7) 20.9 (18.2) 20.3 (17.8) 19.8 (17.2) 19.1 (16.4) 18.4 (15.7) 60 80 20 21.9 (19.2) 21.5 (18.9) 21.1 (18.5) 20.7 (18) 20.1 (17.6) 19.6 (16.9) 18.9 (16.2) 18.2 (15.5) 30 160 40 21.4 (18.8) 21 (18.9) 20.7 (18.5) 20. 2 (17.5) 19.6 (17) 19.1 (16.3) 18.4 (15.8) 17.7 (15) 15 320 80 20.9 (18.2) 20.5 (17.8) 20.2 (17.5) 19.6 (17) 19 (16.5) 18.6 (15.9) 17.9 (15.3) 17.2 (14.6) 8 600 150 20.4 (17.7) 20 (17.3) 19.7 (17) 19 (16.4) 18.5 (15.9) 18.1 (15.3) 17.4 (14.8) 16.6 (13.9) 4 1200 300 19.8 (17.1) 19.4 (16.7) 19 (16.3) 18.3 (15.6) 17.9 (15.2) 17.5 (14.7) 16.8 (14) 16 (13.1) 2 2400 600 19 (16.1) 18.5 (15.5) 18 (15.1) 17.2 (14.2) 16.9 (14) 16.5 (13.6) 15.8 (12.9) 15 (12) 1 4800 1200 16.1 (13.3) 16 (13.2) 15.9 (12.9) 15.5 (12 .6) 15.4 (12.5) 15.1 (12.2) 14.6 (11.7) 13.9 (10.9) data sheet ad7124- 8 rev. b | page 31 of 91 sinc 3 table 19 . rms noise (peak -to - peak noise) vs. gain and output data rate ( v) , mid power mode filter word (dec.) output data rate ( sps ) output data rate (zero latency mode) ( s ps ) f 3db (hz) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 2047 2.34 0.78 0.64 0.25 (1.5) 0.17 (1) 0.087 (0.58) 0.065 (0.4) 0.049 (0.27) 0.034 (0.19) 0.03 (0.16) 0.022 (0.11) 960 5 1.67 1.36 0.35 (2.2) 0.23 (1.3) 0.14 (0.8 2) 0.1 (0.58) 0.074 (0.43) 0.053 (0.31) 0.041 (0.22) 0.034 (0.17) 480 10 3.33 2.72 0.5 (3.1) 0.31 (1.9) 0.19 (1.3) 0.14 (0.89) 0.1 (0.63) 0.075 (0.44) 0.6 (0.35) 0.049 (0.28) 320 15 5 4.08 0.6 (3.8) 0.38 (2.4) 0.24 (1.6) 0.17 (1.1) 0.13 (0.8) 0.089 (0.54 ) 0.076 (0.46) 0.062 (0.35) 160 30 10 8.16 0.83 (5.6) 0.54 (3.3) 0.34 (2.2) 0.24 (1.6) 0.18 (1.1) 0.13 (0.77) 0.1 (0.65) 0.088 (0.53) 96 50 16.67 13.6 1.1 (7.5) 0.72 (4.4) 0.44 (2.9) 0.31 (2) 0.24 (1.5) 0.17 (1) 0.14 (0.82) 0.11 (0.7) 80 60 20 16.32 1.2 (7.7) 0.8 (4.8) 0.48 (3.1) 0.35 (2.2) 0.25 (1.6) 0.18 (1.1) 0.15 (0.94) 0.12 (0.77) 40 120 40 32.64 1.7 (11) 1.1 (7) 0.7 (4.6) 0.47 (3.2) 0.36 (2.2) 0.26 (1.7) 0.21 (1.5) 0.18 (1.1) 20 240 80 65.28 2.5 (16) 1.6 (9.7) 0.94 (6.2) 0.7 (5) 0.53 (3.2) 0.37 ( 2.3) 0.31 (2.1) 0.26 (1.8) 10 480 160 130.6 3.5 (24) 2.2 (15) 1.4 (9.3) 1 (7) 0.78 (5.3) 0.56 (3.9) 0.46 (3.1) 0.38 (2.5) 5 960 320 261.1 6.7 (53) 4.1 (34) 2.5 (19) 1.8 (14) 1.2 (8.7) 0.84 (6.4) 0.67 (5) 0.57 (3.9) 3 1600 533.33 435.2 25 (170) 13 (90) 7 .1 (53) 4.2 (30) 2.4 (18) 1.5 (11) 1.1 (7.8) 0.89 (6.8) 2 2400 800 652.8 110 (740) 54 (360) 27 (200) 14 (110) 7.4 (51) 3.9 (29) 2.3 (16) 1.6 (12) 1 4800 1600 1306 880 (5800) 430 (3100) 220 (1500) 110 (760) 55 (400) 27 (180) 14 (110) 7.5 (56) table 20 . effective resolution (peak-to - peak resolution) vs. gain and output data rate (bits ), mid power mode filter word (dec.) output data rate ( sps ) output data rate (zero latency mode) ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 ga in = 32 gain = 64 gain = 128 2047 2.34 0.78 24 (21.7) 23.8 (21.2) 23.6 (21) 23.2 (20.6) 22.6 (20.1) 22.1 (19.6) 21.3 (18.9) 20.7 (18.4) 960 5 1.67 23.8 (21.1) 23.4 (20.8) 23.1 (20.5) 22.6 (20) 22 (19.5) 21.5 19) 20.8 (18.4) 20.1 (17.8) 480 10 3.33 23.3 (20.6) 22.9 (20.3) 22.6 (19.9) 22.1 (19.4) 21.5 (18.9) 21 (18.4) 20.3 (17.8) 19.6 (17.1) 320 15 5 23 (20.3) 22.6 (20) 22.3 (19.6) 21.8 (19.1) 21.2 (18.6) 20.7 (18.1) 20 (17.4) 19.3 (16.8) 160 30 10 22.5 (19.8) 22.1 (19.5) 21.8 (19.1) 21.3 (18.6) 20.7 (18 .1) 20.2 (17.6) 19.5 (16.9) 18.8 (16.2) 96 50 16.67 22.1 (19.4) 21.7 (19.1) 21.4 (18.7) 20.9 (18.2) 20.3 (17.7) 19.8 (17.2) 19.1 (16.5) 18.4 (15.8) 80 60 20 22 (19.3) 21.6 (19) 21.3 (18.6) 20.8 (18.1) 20.2 (17.6) 19.7 (17.1) 19.1 (16.3) 18.3 (15.6) 40 1 20 40 21.5 (18.8) 21.1 (18.5) 20.8 (18.1) 20.3 (17.6) 19.7 (17.1) 19.2 (16.5) 18.5 (15.7) 17.7 (15.1) 20 240 80 21 (18.3) 20.6 (18) 20.3 (17.6) 19.8 (17) 19.2 (16.6) 18.7 (16) 18 (15.2) 17.2 (14.4) 10 480 160 20.4 (17.7) 20.1 (17.3) 19.8 (17) 19.2 (16.4) 18.6 (15.9) 18.1 (15.3) 17.4 (14.6) 16.7 (13.9) 5 960 320 19.5 (16.5) 19.2 (16.2) 19 (16) 18.4 (15.4) 18 (15.1) 17.5 (14.6) 16.8 (13.9) 16.1 (13.3) 3 1600 533.33 17.6 (14.8) 17.5 (14.8) 17.4 (14.5) 17.2 (14.3) 17 (14.1) 16.7 (13.8) 16.1 (13.3) 15.4 (12. 6) 2 2400 800 15.5 (12.7) 15.5 (12.7) 15.5 (12.6) 15.4 (12.6) 15.4 (12.6) 15.3 (12.4) 15 (12.3) 14.6 (11.7) 1 4800 1600 12.5 (9.7) 12.5 (9.7) 12.5 (9.7) 12.5 (9.7) 12.5 (9.6) 12.5 (9.6) 12.4 (9.5) 12.4 (9.4) post filters table 21 . rms noise (peak -to - peak noise) vs. gain and output data rate (v), mid power mode output data rate ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 16.67 1.1 (6.3) 0.69 (4) 0.41 (2.5) 0.31 (2) 0.23 (1.4) 0.17 (0.96) 0. 13 (0.79) 0.11 (0.61) 20 1.1 (6.9) 0.7 (4) 0.41 (2.5) 0.33 (2.1) 0.23 (1.5) 0.18 (0.96) 0.14 (0.81) 0.12 (0.67) 25 1.2 (8) 0.8 (4.6) 0.46 (2.8) 0.36 (2.3) 0.25 (1.5) 0.17 (1) 0.15 (0.9) 0.12 (0.74) 27.27 1.3 (9.2) 0.82 (4.8) 0.48 (2.8) 0.36 (2.3) 0.28 ( 1.6) 0.19 (1.1) 0.16 (1) 0.13 (0.79) table 22 . effective resolution (peak-to - peak resolution) vs. gain an d output data rate (bits) , mid power mode output data rate ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 16.67 22.1 (19.6) 21.8 (19.2) 21.5 (18.9) 20.9 (18.3) 20.4 (17.8) 19.8 (17.3) 19.2 (16.6) 18.4 (16) 20 22.1 (19.5) 21.8 (19.2) 21.5 (18.9) 20.9 (18.2) 20.4 (17.7) 19.8 (17.3) 19 (16.6) 18.3 (15.8) 25 22 (19.2) 21.6 (19.1) 21.4 (18.8) 20. 7 (18.1) 20.3 (17.6) 19.7 (17.2) 18.9 (16.4) 18.2 (15.7) 27.27 21.9 (19) 21.5 (19) 21.3 (18.8) 20.7 (18.1) 21.1 (17.6) 19.7 (17.1) 18.9 (16.3) 18.2 (15.6) ad7124- 8 data sheet rev. b | page 32 of 91 fast settling filter ( sinc 4 + sinc 1 ) table 23 . rms noise (peak -to - peak noi se) vs. gain and output data rate (v) , mid power mode (average by 16) filter word (dec.) output data rate ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 96 2.63 0.36 (2.4) 0.23 (1.5) 0.15 (0.82) 0.1 (0.71) 0.078 (0.44) 0.056 (0.35) 0.045 (0.26) 0.038 (0.21) 30 8.42 0.67 (4.2) 0.44 (2.7) 0.26 (1.6) 0.18 (1.1) 0.14 (0.8) 0.1 (0.54) 0.08 (0.48) 0.067 (0.41) 6 42.11 1.5 (9) 0.96 (6.1) 0.57 (3.7) 0.42 (2.6) 0.32 (1.9) 0.22 (1.5) 0.18 (1.1) 0.15 (0.95) 5 50.53 1.6 (9.3) 1 (7.7) 0.62 (4) 0.46 (3) 0.33 (2) 0.24 (1.6) 0.2 (1.3) 0.17 (1.2) 2 126.32 2.5 (15) 1.6 (11) 1 (7.2) 0.76 (4.9) 0.57 (3.7) 0.41 (2.7) 0.32 (2.4) 0.29 (1.9) 1 252.63 5.2 (21) 3.1 (19) 1.8 (11) 1.4 (9.8) 0.92 (6.2) 0.62 (4.2) 0.49 (3) 0.41 (3) table 24. effective resolution ( peak -to - peak resolution ) vs. gai n and output data rate (bits) , mid power mode (average by 16) filter word (dec.) output data rate ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 12 8 96 2.63 23.7 (21) 23.4 (20.7) 23 (20.5) 22.5 (19.8) 21.9 (19.4) 21.4 (18.8) 20.7 (18.2) 20 (17.5) 30 8.42 22.8 (20.2) 22.4 (19.8) 22.2 (19.5) 21.7 (19.1) 21 (18.6) 20.6 (18.1) 19.9 (17.3) 19.1 (16.5) 6 42.11 21.7 (19.1) 21.3 (18.6) 21.1 (18.4) 20.5 (1 7.9) 19.9 (17.3) 19.4 (16.7) 18.7 (16) 18 (15.2) 5 50.53 21.5 (19) 21.2 (18.4) 20.9 (18.2) 20.4 (17.8) 19.8 (17.2) 19.3 (16.6) 18.5 (15.9) 17.8 (15) 2 126.32 20.9 (18.3) 20.5 (17.8) 20.2 (17.4) 19.6 (17) 19.1 (16.4) 18.6 (15.8) 17.9 (15.2) 17.1 (14.3) 1 252.63 19.9 (17.3) 19.6 (17) 19.4 (16.8) 18.8 (16) 18.4 (15.6) 17.9 (15.2) 17.3 (14.7) 16.5 (13.7) fast settling filter ( sinc 3 + sinc 1 ) table 25 . rms noise (peak -to - peak noise) vs. gain and output data rate (v) , mid power mode (average by 16) filter word (dec.) output data rate ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 96 2.78 0.39 (2.4) 0.25 (1.5) 0.16 (1) 0.11 (0.67) 0.08 (0.48) 0.058 (0.31) 0.047 (0.27) 0.039 (0.23) 30 8.89 0.71 (4.2 ) 0.43 (2.5) 0.27 (1.6) 0.19 (1.1) 0.15 (1) 0.098 (0.64) 0.083 (0.47) 0.068 (0.4) 6 44.44 1.5 (9.5) 0.93 (6) 0.59 (3.8) 0.43 (2.6) 0.32 (2.1) 0.22 (1.5) 0.18 (1.1) 0.15 (0.98) 5 53.33 1.6 (11) 1 (6.9) 0.66 (4.2) 0.46 (2.8) 0.35 (2.3) 0.24 (1.6) 0.2 (1.2) 0.17 (1.1) 2 133.33 6 (37) 3.2 (20) 1.8 (11) 1 (7.2) 0.63 (4.5) 0.31 (3) 0.33 (2.2) 0.27 (1.8) 1 266.67 44 (320) 23 (160) 12 (83) 5.7 (41) 3 (20) 1.6 (9.9) 0.84 (6.4) 0.56 (3.5) table 26. effective resolution ( peak -to - peak reso lution ) vs. gai n and output data rate (bits) , mid power mode (average by 16) filter word (dec.) output data rate ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 96 2.78 23.6 (21) 23.3 (20.7) 22.9 (20.3) 22.5 (19.8) 21.9 (19.3) 21.4 (18.9) 20.7 (18.1) 19.9 (17.4) 30 8.89 22.7 (20.2) 22.5 (19.9) 22.2 (19.6) 21.7 (19.1) 21 (18.3) 20.6 (17.9) 19.8 (17.3) 19.1 (16.6) 6 44.44 21.7 (19) 21.4 (18.7) 21 (18.3) 20.5 (17.9) 19.9 (17.2) 19.4 (16.7) 18.7 (16.1) 18 (15.3) 5 53.33 2 1.5 (18.8) 21.2 (18.5) 20.9 (18.2) 20.4 (17.8) 19.8 (17.1) 19.3 (16.6) 18.6 (16) 17.8 (15.1) 2 133.33 19.7 (17) 19.6 (16.9) 19.4 (16.8) 19.2 (16.4) 18.9 (16.1) 18.5 (15.7) 17.8 (15.1) 17.1 (14.4) 1 266.67 16.8 (13.9) 16.7 (13.9) 16.7 (13.9) 16.7 (13.9) 16.7 (13.9) 16.6 (13.9) 16.5 (13.6) 16.1 (13.4) data sheet ad7124- 8 rev. b | page 33 of 91 low power mode sinc 4 table 27 . rms noise (peak -to - peak noise ) vs. gain and output data rate ( v) , low power mode filter word (dec.) output data rate ( sps ) output data rate (zero late ncy mode) ( sps ) f 3db (hz) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 2047 1.17 0.293 0.269 0.22 (1.2) 0.15 (0.89) 0.095 (0.67) 0.071 (0.41) 0.053 (0.26) 0.043 (0.2) 0.035 (0.16) 0.024 (0.12) 1920 1.25 0.3125 0.288 0.24 ( 1.5) 0.15 (0.89) 0.095 (0.67) 0.071 (0.41) 0.053 (0.26) 0.043 (0.2) 0.035 (0.16) 0.024 (0.12) 960 2.5 0.625 0.575 0.37 (2.1) 0.23 (1.2) 0.13 (0.82) 0.1 (0.61) 0.068 (0.37) 0.055 (0.26) 0.041 (0.23) 0.035 (0.17) 480 5 1.25 1.15 0.5 (3) 0.3 (1.7) 0.18 (1.2 ) 0.13 (0.77) 0.099 (0.56) 0.078 (0.39) 0.06 (0.31) 0.052 (0.26) 240 10 2.5 2.3 0.65 (4.1) 0.42 (2.5) 0.26 (1.9) 0.2 (1.1) 0.14 (0.8) 0.1 (0.6) 0.085 (0.5) 0.072 (0.43) 120 20 5 4.6 0.9 (5.8) 0.61 (3.5) 0.38 (2.5) 0.28 (1.7) 0.2 1.2) 0.15 (0.85) 0.12 (0. 68) 0.096 (0.6) 60 40 10 9.2 1.3 (8) 0.82 (5) 0.53 (3.7) 0.38 (2.4) 0.29 (1.8) 0.21 (1) 0.17 (0.95) 0.14 (0.9) 48 50 12.5 11.5 1.4 (9.3) 0.95 (6) 0.6 (4.2) 0.46 (2.8) 0.32 (2.1) 0.24 (1.5) 0.2 (1.1) 0.16 (1) 40 60 15 13.8 1.6 (10) 0.99 (6.6) 0.64 (4.5) 0.47 (3.2) 0.35 (2.2) 0.26 (1.7) 0.21 (1.3) 0.17 (1.1) 30 80 20 18.4 1.8 (12) 1.2 (7.5) 0.77 (5.1) 0.55 (3.7) 0.4 (2.7) 0.3 (2) 0.25 (1.6) 0.19 (1.3) 15 160 40 36.8 2.6 (17) 1.8 (11) 1.1 (7.2) 0.85 (5.7) 0.56 (3.9) 0.41 (2.5) 0.33 (2.1) 0.28 (1.6) 8 300 75 69 3.7 (24) 2.5 (17) 1.6 (11) 1.2 (7.5) 0.87 (5.6) 0.58 (3.9) 0.48 (2.9) 0.39 (2.6) 4 600 150 138 5.2 (35) 4 (24) 2.6 (17) 2.1 (13) 1.4 (8.5) 1 (6) 0.76 (5.2) 0.6 (3.9) 2 1200 300 276 9.4 (57) 7.6 (47) 5.8 (36) 4.9 (32) 3 (19) 1.9 (11) 1.4 (9) 1.3 (7 .8) 1 2400 600 552 72 (470) 39 (240) 22 (130) 16 (110) 8 (49) 4.8 (29) 3.3 (21) 2.6 (18) table 28 . effective resolution (peak-to - peak resolution) vs. gain and output d a ta rate , low power mode filter word (dec.) output data rate ( s ps ) output data rate (zero latency mode) ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 2047 1.17 0.29311 24 (21.7) 23.8 (21.4) 23.7 (20.9) 23.2 (20.5) 22.7 (20.2) 21.8 (19.7) 21.3 (18.9) 20.6 (18.3) 1920 1.25 0.3125 2 4 (21.7) 23.8 (21.3) 23.6 (20.8) 23.1 (20.5) 22.6 (20.1) 21.8 (19.6) 21.2 (18.9) 20.6 (18.3) 960 2.5 0.625 23.7 (21.2) 23.4 (21) 23.2 (20.5) 22.6 (20) 22.1 (19.7) 21.4 (19.2) 20.8 (18.4) 20.1 (17.8) 480 5 1.25 23.3 (20.7) 23 (20.5) 22.7 (20) 22.1 (19.6) 21.6 (19.1) 20.9 (18.6) 20.3 (17.9) 19.5 (17.2 240 10 2.5 22.9 (20.2) 22.5 (19.9) 22.2 (19.4) 21.6 (19.1) 21.1 (18.6) 20.5 (18) 19.8 (17.2) 19.1 (16.5) 120 20 5 22.4 (19.7) 22 (19.4) 21.7 (18.9) 21.1 (18.5) 20.6 (18) 20 (17.5) 19.3 (16.8) 18.6 (16) 60 4 0 10 21.9 (19.2) 21.5 (18.9) 21.2 (18.4) 20.6 (18) 20.1 (17.4) 19.5 (16.9) 18.8 (16.3) 18.1 (15.4) 48 50 12.5 21.7 (19) 21.3 (18.7) 21 (18.2) 20.4 (17.8) 19.9 (17.2) 19.3 (16.7) 18.6 (16.1) 17.9 (15.2) 40 60 15 21.6 (18.9) 21.2 (18.5) 20.9 (18.1) 20.3 (1 7.6) 19.8 (17.1) 19.2 (16.5) 18.5 (15.9) 17.8 (15.1) 30 80 20 21.4 (18.7) 21 (18.3) 20.6 (17.9) 20.1 (17.4) 19.6 (16.8) 19 (16.2) 18.3 (15.6) 17.6 (14.9) 15 160 40 20.9 (18.2) 20.4 (17.8) 20.1 (17.4) 19.5 (16.8) 19.1 (16.3) 18.5 (15.7) 17.8 (15.2) 17.1 ( 14.5) 8 300 75 20.4 (17.7) 19.9 (17.2) 19.6 (16.8) 19 (16.3) 18.5 (15.8) 18 (15.3) 17.3 (14.7) 16.6 (13.9) 4 600 150 19.9 (17.1) 19.3 (16.7) 18.9 (16.2) 18.2 (15.6) 17.8 (15.2) 17.3 (14.7) 16.7 (13.9) 16 (13.3) 2 1200 300 19 (16.4) 18.3 (15.7) 17.7 (15. 1) 17 (14.3) 16.7 (14) 16.3 (13.8) 15.7 (13.1) 14.9 (12.3) 1 2400 600 16.1 (13.4) 16 (13.4) 15.8 (13.3) 15.3 (12.5) 15.2 (12.5) 15 (12.4) 14.5 (11.9) 13.9 (11) ad7124- 8 data sheet rev. b | page 34 of 91 sinc 3 table 29. rms noise (peak -to - peak noise ) vs. gain and output dat a rate ( v) , low power mode filter word (dec.) output data rate ( sps ) output data rate (zero latency mode) ( sps ) f 3db (hz) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 2047 1.17 0.39 0.32 0.26 (1.5) 0.17 (0.9) 0.099 (0.6) 0.072 (0.36) 0.055 (0.27) 0.039 (0.21) 0.032 (0.16) 0.026 (0.13) 480 5 1.67 1.36 0.51 (3.1) 0.31 (1.9) 0.2 (1.3) 0.15 (0.86) 0.11 (0.65) 0.078 (0.45) 0.063 (0.37) 0.05 (0.28) 240 10 3.33 2.72 0.75 (4.5) 0.45 (2.8) 0.29 (2) 0.21 (1.3) 0.16 (0.9) 0.11 (0 .65) 0.085 (0.51) 0.071 (0.39) 160 15 5 4.08 0.88 (5.5) 0.55 (3.3) 0.3 (2.4) 0.26 (1.6) 0.19 (1.2) 0.14 (0.79) 0.1 (0.62) 0.089 (0.53) 80 30 10 8.16 1.3 (7.8) 0.77 (4.9) 0.47 (3.3) 0.36 (2.2) 0.27 (1.7) 0.19 (1.2) 0.15 (0.94) 0.12 (0.72) 48 50 16.67 13. 6 2.7 (9.9) 1 (6.4) 0.63 (4.6) 0.47 (3.1) 0.36 (2.2) 0.26 (1.7) 0.2 ( 1.3) 0.16 (1) 40 60 20 16.32 1.8 (12) 1.1 (7) 0.71 (5) 0.52 (3.4) 0.39 (2.5) 0.27 (1.8) 0.21 (1.4) 0.18 (1.3) 20 120 40 32.64 2.5 (17) 1.6 (10) 0.9 (6.1)7 0.73 (5) 0.55 (3.7) 0.41 (2.5 ) 0.3 (1.9) 0.26 (1.6) 10 240 80 65.28 3.5 (25) 2.4 (16) 1.5 (9.9) 1.1 (7.6) 0.8 (5.3) 0.56 (3.5) 0.45 (2.8) 0.37 (2.3) 5 480 160 130.6 6.8 (48) 4.3 (32) 2.6 (19) 2 (15) 1.3 (9) 0.9 (6.5) 0.7 (4.5) 0.55 (3.3) 3 800 266.67 217.6 25 (180) 13 (98) 7.4 (53) 4.5 (34) 2.7 (18) 1.6 (11) 1.1 (7.7) 0.91 (6) 2 1200 400 326.4 110 (740) 55 (390) 28 (180) 15 (100) 7.6 (57) 4 (32) 2.4 (16) 1.6 (12) 1 2400 800 652.8 870 (5600) 430 (2900) 220 (1400) 110 (670) 56 (370) 28 (180) 14 (100) 7.6 (52) table 30. effective resolution (peak -to - peak resolution) vs. gain and output d a ta rate , low power mode filter word (dec.) output data rate ( sps ) output data rate (zero latency mode) ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 2047 1.17 0.39 24 (21.7) 23.8 (21.4) 23.6 (21) 23 (20.7) 22.4 (20.1) 21.9 (19.5) 21.2 (18.9) 20.5 (18.2) 480 5 1.67 23.2 (20.6) 22.9 (20.3) 22.6 (19.9) 22 (19.5) 21.4 (18.9) 20.9 (18.4) 20.2 (17.7) 19.6 (17.1) 240 10 3.33 22.7 (20.1) 22.4 (19 .8) 22.1 (19.3) 21.5 (18.9) 20.9 (18.4) 20.4 (17.9) 19.8 (17.2) 19.1 (16.6) 160 15 5 22.4 (19.8) 22.1 (19.5) 21.8 (19) 21.2 (18.6) 20.6 (18) 20.1 (17.6) 19.5 (16.9) 18.8 (16.2) 80 30 10 21.9 (19.3) 21.6 (19) 21.3 (18.5) 20.7 (18.1) 20.1 (17.5) 19.6 (17) 19 (16.3) 18.3 (15.7) 48 50 16.67 21.5 (18.9) 21.2 (18.6) 20.9 (18.1) 20.3 (17.6) 19.7 (17.1) 19.2 (16.5) 18.6 (15.9) 17.9 (15.2) 40 60 20 21.4 (18.7) 21.1 (18.4) 20.8 (17.9) 20.2 (17.5) 19.6 (16.9) 19.1 (16.4) 18.5 (15.8) 17.7 (15.1) 20 120 40 20.9 (18 .2) 20.6 (17.9) 20.3 (17.4) 19.7 (16.9) 19.1 (16.4) 18.6 (15.9) 18 (15.3) 17.2 (14.6) 10 120 80 20.4 (17.6) 20 (17.2) 19.7 (16.9) 19.1 (16.3) 18.6 (15.9) 18.1 (15.4) 17.4 (14.8) 16.7 (14.1) 5 480 160 19.5 (16.7) 19.2 (16.3) 18.8 (16) 18.2 (15.4) 17.9 (15 .1) 17.4 (14.6) 16.8 (14.1) 16.1 (13.5) 3 800 266.67 17.6 (14.8) 17.5 (14.6) 17.4 (14.5) 17.1 (14.2) 16.8 (14.1) 16.6 (13.8) 16.1 (13.3) 15.4 (12.7) 2 1200 400 15.5 (12.7) 15.5 (12.7) 15.4 (12.7) 15.4 (12.6) 15.3 (12.4) 15.2 (12.3) 15 (12.2) 14.5 (11.6) 1 2400 800 12.5 (9.8) 12.5 (9.8) 12.5 (9.8) 12.5 (9.8 12.5 (9.7) 12.5 (9.7) 12.5 (9.6) 12.3 (9.6) p ost filters table 31 . rms noise (peak -to - peak noise) vs. gain and output data rate (v), low power mode output data rate ( sps ) gai n = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 16.67 1.7 (12) 0.96 (5.8) 0.65 (4) 0.45 (2.6) 0.34 (1.9) 0.25 (1.5) 0.2 (1.2) 0.16 (0.92) 20 1.7 (11) 1.1 (6.4) 0.65 (4.2) 0.46 (2.6) 0.36 (1.9) 0.26 (1.5) 0.21 (1.2) 0.17 (0.93) 25 1.8 (11) 1.1 (6.7) 0.68 (4.2) 0.52 (2.7) 0.37 (2) 0.26 (1.6) 0.22 (1.2) 0.17 (1.1) 27.27 1.9 (11) 1.1 (7.3) 0.69 (4.4) 0.54 (2.9) 0.4 (2.1) 0.27 (1.8) 0.23 (1.4) 0.18 (1.3) table 32 . effective resolution (peak-to - peak resoluti on) vs. gain an d output data rate (bits) , low power mode output data rate ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 16.67 21.5 (18.8) 21.3 (18.7) 20.9 (18.2) 21.4 (17.9) 19.8 (17.3) 19.3 (16.7) 18.6 (16.1) 17.9 (15 .4) 20 21.5 (18.8) 21.2 (18.6) 20.9 (18.2) 20.4 (17.9) 19.7 (17.3) 19.2 (16.7) 18.6 (16.1) 17.8 (15.4) 25 21.4 (18.8) 21.2 (18.5) 20.8 (18.2) 20.2 (17.8) 19.7 (17.3) 19.2 (16.6) 18.5 (15.9) 17.8 (15.1) 27.27 21.3 (18.7) 21.1 (18.4) 20.8 (18.1) 20.2 (17 .7) 19.6 (17.2) 19.1 (16.4) 18.4 (15.8) 17.7 (14.9) data sheet ad7124- 8 rev. b | page 35 of 91 fast settling filter ( sinc 4 + sinc 1 ) table 33 . rms noise (peak -to - peak noise) vs. gain and output data rate (v) , low power mode (average by 8) filter word (dec.) output data rat e ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 96 2.27 0.53 (3.4) 0.34 (2.2) 0.19 (1.2) 0.16 (0.97) 0.1 (0.61) 0.082 (0.48) 0.065 (0.38) 0.058 (0.37) 30 7.27 0.89 (5.4) 0.6 (3.6) 0.36 (2.2) 0.27 (1.8) 0.21 (1.2) 0.15 (0.93) 0.12 (0.65) 0.093 (0.59) 6 36.36 2.1 (12) 1.4 (8.3) 0.82 (5.6) 0.64 (3.9) 0.43 (2.7) 0.33 (2.1) 0.25 (1.6) 0.21 (1.4) 5 43.64 2.2 (13) 1.4 (9.7) 0.93 (6.5) 0.71 (4.2) 0.5 (3.1) 0.35 (2.4) 0.28 (1.7) 0.23 (1.5) 2 109.1 3.7 (25) 2.5 (18) 1.5 (10) 1.3 (7.5) 0.86 (5.6) 0.59 (3.5) 0.47 (3.2) 0.39 (2.4) 1 218.18 8.4 (52) 5.4 (34) 3.3 (21) 2.6 (16) 1.6 (9.8) 0.97 (6.1) 0.75 (5.4) 0.63 (4.7) table 34. effective resolution ( peak -to - peak resolution ) vs. gai n and output data rate ( bits) , low power mode (average by 8) filter word (dec.) output data rate ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 96 2.27 23.2 (20.5) 22.8 (20.1) 22.7 (20) 21.9 (19.3) 21.5 (19) 20.9 (18.3) 20.2 (17.6) 19.4 (16.7 ) 30 7.27 22.4 (19.8) 22 (19.4) 21.7 (19.1) 21.1 (18.4) 20.5 (18) 20 (17.4) 19.4 (16.9) 18.7 (16) 6 36.36 21.2 (18.6) 20.8 (18.1) 20.5 (17.8) 19.9 (17.3) 19.5 (16.8) 18.9 (16.2) 18.3 (15.6) 17.5 (14.8) 5 43.64 21.1 (18.5) 20.7 (18) 20.4 (17.6) 19.8 (17. 2) 19.3 (16.6) 18.8 (16) 18.1 (15.5) 17.4 (14.7) 2 109.1 20.4 (17.6) 19.9 (17.1) 19.6 (16.9) 18.9 (16.3) 18.5 (15.8) 18 (15.4) 17.3 (14.6) 16.6 (14) 1 218.18 19.2 (16.6) 18.8 (16.2) 18.5 (15.9) 17.9 (15.2) 17.6 (15) 17.3 (14.7) 16.7 (13.8) 15.9 (13) f ast settling filter ( sinc 3 + sinc 1 ) table 35 . rms noise (peak -to - peak noise) vs. gain and output data rate (v) , low power mode (average by 8) filter word (dec.) o utput data rate ( sps ) gain = 1 gain = 2 gain = 4 gain = 8 gain = 16 g ain = 32 gain = 64 gain = 128 96 2.5 0.53 (3.6) 0.33 (2.1) 0.21 (1.4) 0.15 (0.93) 0.11 (0.6) 0.073 (0.44) 0.064 (0.39) 0.051 (0.29) 30 8 0.92 (5.4) 0.58 (3.4) 0.4 (2.3) 0.28 (1.6) 0.2 (1.1) 0.14 (0.79) 0.11 (0.62) 0.094 (0.51) 6 40 2.1 (13) 1.3 (8.3) 0. 83 (6) 0.61 (4.1) 0.44 (3) 0.33 (2.1) 0.26 (1.6) 0.21 (1.3) 5 48 2.3 (14) 1.5 (8.6) 0.87 (6.6) 0.7 (4.4) 0.5 (3.3) 0.36 (2.3) 0.3 (1.7) 0.23 (1.4) 2 120 11 (72) 5.9 (39) 3.2 (23) 1.9 (15) 1.1 (8.5) 0.7 (4.7) 0.5 (3.3) 0.4 (2.4) 1 240 88 (530) 45 (250) 2 2 (140) 11 (82) 5.8 (40) 3 (22) 01.6 (11) 0.94 (6.3) table 36. effective resolution ( peak -to - peak resolution ) vs. gai n and output data rate (bits) , low power mode (average by 8) filter word (dec.) output data rate ( sps ) gain = 1 g ain = 2 gain = 4 gain = 8 gain = 16 gain = 32 gain = 64 gain = 128 96 2.5 23.2 (20.4) 22.8 (20.2) 22.5 (19.8) 22 (19.4) 21.4 (19) 21 (18.4) 20.2 (17.6) 19.6 (17) 30 8 22.4 (19.8) 22 (19.5) 21.6 (19) 21.1 (18.6) 20.6 (18.1) 20.1 (17.6) 19.4 (16.9) 18.7 (1 6.2) 6 40 21.2 (18.6) 20.9 (18.2) 20.5 (17.7) 20 (17.2) 19.4 (16.7) 18.9 (16.2) 18.2 (15.6) 17.5 (14.9) 5 48 21 (18.4) 20.7 (18.1) 20.4 (17.5) 19.8 (17) 19.3 (16.5) 18.7 (16.1) 18 (15.5) 17.4 (14.8) 2 120 18.7 (16.1) 18.7 (16) 18.6 (15.8) 18.3 (15.3) 1 8.1 (15.2) 17.8 (15) 17.3 (14.6) 16.6 (14) 1 240 15.8 (13.2) 15.8 (13.2) 15.8 (13.2) 15.7 (12.9) 15.7 (12.9) 15.7 (12.8) 15.6 (12.8) 15.3 (12.6) ad7124- 8 data sheet rev. b | page 36 of 91 getting started 13048-068 v bias seria l inter f ace and contro l logic interna l clock diagnostics channe l sequencer digi t al fi l ter clk av dd ain0 x-mux a v dd a v dd reference detect dout/rd y sclk cs iov dd vdd tem p sensor din sync a v ss notes 1. simplified block diagram shown. a v ss psw out+ out? in+ in? refin1(?) refin1(+) r ref out+ out? in+ in? ain1 ain2 ain3 ain12 ain13 refin2(+) refin2(?) pga - adc ad7124-8 regca p a regcapd a v ss dgnd figure 64 . basic connection diagram overview the ad7124 - 8 is a low power adc that incorporate s a - modu - lator, buffer, reference, gain stage , and on - chip digital filtering, which is intended for the measurement of wide dynamic range s , low frequency signals (such as those in pressure transducers), weigh scales, and temperature measurement application s. power modes the ad7124 - 8 offers three power modes: high power mode, mid power mode , and low power mode. this allows the user total flexibility in terms of speed, rms noise , and current con sumption. analog inputs the device can have 8 differential or 15 pseudo differentia l analog inputs. the analog inputs can be buffered or unbuffered. the ad7124 - 8 uses flexible multiplexing ; th us , any analog input pin can be selected as a positive input ( ainp ) and any analog input pin can be selected as a negative input ( ainm ) . multiplexer the on - chip multiplexer increases the channel count of the device . because the multiplexer is included on c hip, any channel changes are synchronized with the conversion process. reference the device contains a 2.5 v reference , which has a drift of 1 5 ppm/c max imum . reference buffers are also included on chip , which can be used with the internal reference and externally applied references. programmable gain array ( pga ) the analog input signal can be amplified using the pga. the pga allows gains of 1, 2, 4, 8, 16, 32, 64, and 128. burnout currents two burnout currents , which can be programmed to 500 na, 2 a , o r 4 a, are included on chip to detect the presence of the external sensor. - adc and filter t he ad7124 - 8 contains a fourth - order - modulator followed by a digital filter. t he device has the following filter options: ? s inc 4 ? s inc 3 ? fast f ilter ? post f ilter ? zero laten cy channel sequencer the ad7124 - 8 allows up to 16 confi gurations, or channels. these channels can consist of analog inputs, reference inputs , or power supplies such that diagnostic functions , such as power supply monitoring , can be interleaved with conversions. the sequencer automatically converts all enabled channels. when each enabled channel is selected, the time required to generate t he conversion is equal to the settling time for the sele cted channel. per channel configuration the ad7124 - 8 allows up to eight different setups, e a ch setup consisting of a gain, output data rate, filte r type, and a reference source. each channel i s then linked to a setup. data sheet ad7124- 8 rev. b | page 37 of 91 serial int erface the ad7124 - 8 has a 3 - wire or 4 - wire spi. the on - chip registers are accessed via the serial interface. c lock the device has an internal 614.4 k hz clo ck. use e ither this clock or an external clock as the clock source for the device . the internal clock can also be made available on a pin if a clock source is required for external circuitry. temperature sensor the on - chip temperature sensor monitors the die temperature. digital outputs the ad7124 - 8 has four general - purpose digital outputs. these can be used for driving external circuitry. for example, an external multiplexer can be controlle d by these outputs. calibration both internal calibration and system calibration are included on chip; therefore, the user has the option of removing offset or gain errors internal to the device only, or removing the offset or gain errors of the complete end system. excitation currents the device contains two excitation currents that can be s et independently to 50 a, 100 a, 2 5 0 a, 500 a, 750 a , or 1 ma. bias voltage a bias voltage generator is included on chip so that signals from thermocouples can be biased suitably. the bias voltage is set to av dd /2 and can be made available on any input. it can supply multiple channels. bridge power switch (p sw) a low - side power switch allows the user to power down bridges that are interfaced to the adc. diagnostics the ad7124 - 8 includes numerous diagnostics features such as ? reference d etect ion ? overvoltage/undervoltage d etect ion ? crc on spi communications ? crc on the memory m ap ? spi read/write checks these diagnostics allow a high level of fault coverage in an applic ation. power supplies the ad7124 - 8 operates with an analog power supply voltage from 2.7 v to 3.6 v in low or mid power mode and f rom 2.9 v to 3.6 v in full power mode. the device accepts a digital power supply from 1.65 v to 3.6 v. the device has two independent power supply pins: av dd and io v dd . ? av dd is referred to av ss . av dd powers the internal analog regulator that supplies th e adc. ? io v dd is refe rred to dgnd. this supply sets the interface logic levels on the spi interface and powers an internal regulator for opera tion of the digital processing. single supply operation ( av ss = dgnd) when the ad7124 - 8 is powered from a single supply that is connected to av dd , av ss and dgnd can be shorted together on one single ground plane. with this setup, an external level shifting circuit is required when using truly bipolar input s to shift the common - mode voltage. recommended regulators include the adp162 , which has a low quiescent current. split supply operation ( av ss dgnd ) the ad7124 - 8 can operate with av ss set to a negative voltage, allowing true bipolar inputs to be applied. this allows a truly fully differential input signal centered around 0 v to be applied to the ad7124 - 8 without the need for an external level shifting circuit. for example, with a 3.6 v split supply, av dd = + 1.8 v and av ss = ?1.8 v. in this use case, the ad7124 - 8 - internally level shifts the signals, allowing the digital output to function between dgnd (nominally 0 v) and io v dd . whe n using a split supply for av dd and av ss , the absolute maximum ratings must be considered ( see the absolute maximum ratings section). ensure that io v dd is set below 3. 6 v to stay within the absolute maximum rating s for the device. digital com munication the ad7124 - 8 has a 3 - wire or 4 - wire spi interface that is compatible with qspi, mi crowire, and dsps. the interface operates in spi mode 3 and can be operated with cs tied low. in s pi mode 3, sclk idles high, the falling edge of sclk is the drive edge, and the rising edge of sclk is the sample edge. this means that data is clocked out on the falling/drive edge and data is clocked in on the rising/sample edge. drive edge sample edge 13048-069 figure 65 . spi mode 3 , sclk edges accessing the adc register map the communications register controls access to the full register map of the adc. this register is an 8 - bit , write only register. on power - up or after a reset, the digital interface default s to a state where it expect s a write to the communications register; therefore, all communication begins by writing to the communications register. ad7124- 8 data sheet rev. b | page 38 of 91 the data written to the communications register determines which register is accessed and if the next oper ation is a read or write. the register address bits ( bit 5 to bit 0) determine the specific register to which the read or write operation applies. when the read or write operation to the selected register is complete, the interface returns to its default s tate, where it expects a write operation to the communications register. in situations where interface synchronization is lost, a write operation of at least 64 serial clock cycles with din high returns the adc to its default state by resetting the entire device , including t he register contents. alternatively, if cs is used with the digital interface, returning cs high resets the digital interface to its default state and aborts any current operation. figure 66 and figure 67 illustrate writing to and reading from a register by first writing the 8 - bit command to the communications register followed by the data for the addressed re gister. rea ding the id register is the recommended method for verifying correct communication with the device . the id register is a read only register and contains the value 0x12 for th e ad7124 - 8 . the co mmunication register and id register details are described in table 37 and table 38. din sclk cs 8-bit command 8 bits, 16 bits, or 24 bits of data cmd dat a 13048-070 figure 66 . writing to a register (8- bit command with regis ter address followed by data of 8 bits , 16 bits , or 24 bits; data length is dependent on the register selected) din sclk cs 8-bit command 8 bits, 16 bits, 24 bits, or 32 bits output cmd dat a dout/rd y 13048-071 figure 67 . reading from a regi ster (8- bit command with register address followed by data of 8 bits , 16 bits , 24 bits , or 32 bits ; data length on dout is dependent on the regi ster selected , crc e nabled ) table 37 . communications register reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 comms [7:0] w en r/ w rs[5:0] 0x00 w table 38 . id register reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x05 id [7:0] device_id silicon_revision 0x 12 r data sheet ad7124- 8 rev. b | page 39 of 91 configuration overvi ew after pow er - on or reset, the ad7124 - 8 default configuration is as follows: ? channel : c hannel 0 is enabled, ain 0 is selected as the positive input, and ain 1 is selected as the negative input . setup 0 is selected . ? setup : t he input and reference buffers are disabled, the gain is set to 1 , and the external reference is selected. ? adc c ontrol : t he ad7124 - 8 is in l ow power mode, continuous convers ion mode and the internal oscillator is enabled and selected as the master clock source. ? diagnostics : t he only diagnostic enabled is the spi_ignore_err function. note that only a few of the register setting options are shown; this list is just an example. for full register information, see the on - chip registers section. figure 68 show s an overview of the suggested flow for changing the adc configuration , divided into the fo llowing three blocks: ? channel configuration (see box a in figure 68) ? s etup ( see box b in figure 68) ? diagnostics ( see box c in figu re 68) ? adc control (see box d in figure 68) channel configuration the ad7124 - 8 has 16 independent analog input channels and eight independent setups . the user can select any of the analog input pairs on any channel, as well as any of the eight setups for any channel, giving the user full flexibility in the channel configura - tion . this also allow s per channel configuration when using all differential in puts because each channel can have its own dedicated setup. along with the analog inputs, signals such as the power supply or reference can also be used as inputs ; they are routed to the multiplexer internally when selected. the ad7124 - 8 allows the user to define 16 configurations , or channels , to the adc. this allows diagnostics to be interleaved with conversions. channel register s use t he channel register s to select which input pins are eith er the positive analog input or the negative analog input for that channel. this register also contains a channel enable/disable bit and the setup selection bits, which are used to select which of the eight available setups to use for this channel. when t he ad7124 - 8 is operating with more than one channel enabled, the channel sequencer cycles through the enabled channels in sequential order, from channel 0 to channel 15 . if a channel is disabl ed, it is skipped by the sequencer. details of t he channel register for channel 0 are shown in table 39. diagnostics enable crc, spi read and write checks enable ldo checks, and more setu p 8 possible adc setups select fi l ter, output d at a r a te, gain and more channe l configur a tion select positive and neg a tive input for each adc channe l select one of 8 setups for adc channe l a b c adc contro l select adc oper a ting mode, clock source, select power mode, d at a + s ta tus, and more d 13048-072 figure 68 . suggested adc configuration flow table 39. c han nel 0 register reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x 09 c hannel _ 0 [15:8] e nable s etup 0 ainp [4:3] 0x800 1 rw [7:0] ainp [2:0] ain m [4:0] ad7124- 8 data sheet rev. b | page 40 of 91 adc setups th e ad7124 - 8 h as eight inde pendent setups . each setup consists of the following four registers: ? c onfiguration r egister ? f ilter r egister ? offset r egister ? gain r egister for example, setup 0 consists of configuration r egister 0, filter register 0, offset regi ster 0, and gain register 0. figure 69 show s the grouping of these registers . the setup is selectable from the channel registers detailed in the channel configuration section. this allows each channel to be assigned to one of eight separate setups. table 40 t hrough table 43 show the four registers that are associated with setup 0. this structure is repeated for setup 1 to s etup 7. configuration register s the c onfiguration registers allow the user to select the output coding of the adc by selecting between bipolar and unipolar. in bipolar mode, the adc accepts negative differential input voltages, and the output coding is off set binary. in unipolar mode, the adc accepts only positive differential voltages, and the coding is straight binary. in either case, the input voltage must be within the av dd and av ss supply voltages. the user can also select the reference source using th ese register s. four options are available : an internal 2.5 v reference, an external reference connected between ref in1( + ) and ref in1( ? ) , an external reference connected between refin2(+) and refin2( ? ) , or av dd to av ss . the pga gain is also set ; g ains of 1, 2, 4, 8, 16, 32, 64 , and 128 are provided. the analog input buffers and reference input buffers for the setup can also be enabled using this register. filter register s the filter register s select which digital filter is used at the output of the adc modul ator. the filter type and the output data rate are selected by setting the bits in this register. for more information , see the digital filter section. configur a tion registers filter registers offset registers gain registers select peripheral functions for adc channel select digital filter type and output data rate analog input buffers reference buffers burnout reference source gain sinc 4 sinc 3 sinc 4 + sinc 1 sinc 3 + sinc 1 enhanced 50hz/60hz rejection gain correction optionally programmed per setup as required offset correction optionally programmed per setup as required 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 config_3 config_5 config_6 config_7 config_4 config_0 config_2 config_1 filter_3 filter_5 filter_6 filter_7 filter_4 filter_0 filter_2 filter_1 gain_3 gain_5 gain_6 gain_7 gain_4 gain_0 gain_2 gain_1 offset_3 offset_5 offset_6 offset_7 offset_4 offset_0 offset_2 offset_1 13048-073 figure 69 . adc setup register grouping table 40. configuration 0 register reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x 19 c onfig _ 0 [15:8] 0 b ipolar b urnout ref_bufp 0x0860 rw [7:0] ref_bufm ain_bufp ain_bufm ref_sel pga table 41. filter 0 register reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x28 f ilter _0 [23 : 9 ] f ilter rej60 post_filter single_cycle 0x0 60180 rw [15:8] 0 fs[10:8] [7:0] fs[7:0] table 42. offset 0 register reg . name bits bit s [23:0] reset rw 0x 29 o ffset _0 [23: 0 ] o ffset [23:0 ] 0x800000 rw table 43. gain 0 register reg . name bits bit s [23:0] reset rw 0x3 1 g ain _0 [23: 0 ] g ain [23:0 ] 0x5xxxx x rw data sheet ad7124- 8 rev. b | page 41 of 91 offset register s the offset regi ster s hold the offset calibration coefficient for the adc. the power - on reset value of an offset register is 0x800000. the offset register s are 24- bit read/write register s . the power - on reset value is automatically overwritten if an internal or system zero - scale calibration is initiated by the user or if the offset registers are written to by the user. gain register s the gain register s are 24- bit register s that hold the gain calibration coefficient for the adc. the gain registers are read/write registers. the gain is factory calibrated at a gain of 1 ; thus , the default value var ies from device to device . the default value is automatically overwritten if a n internal or system full - scale calibrat ion is initiated by the user. for more information on calibratio n, see the calibration sectio n. diagnostics the e rror _e n register enables and disables the numerous diagnostics on the ad7124 - 8 . by default, the spi_ignore function i s enabled , which indicates inappropriate times to communicate with the adc (for example, during power - up and during a reset). other diagnostics include ? spi r ead and w rite checks , which ensure that on ly valid registers are accessed ? sclk counter , which ensur es that the correct number of sclk pulses are used ? spi crc ? memory m ap crc ? ldo c hecks when a diagnostic is enabled, the corresponding flag is contained in the e rror register. all enabled flags are or ed to control the err flag in the s tatus register. thus , if an error occurs (for example , the spi crc check detects an error), the relevant flag (for example, the spi_crc_err flag ) in the e rror register is set. the err flag in the s tatus register is also set. this is useful when the status bits are appended to conversions. the err bit indicates if an error has occurred. the user can then read the e rror register for more detail s on the error source. the frequency of the on - chip oscillator can also be monitored on the ad7124 - 8 . the mclk_c ount register monitors the master clock pulses. table 44 to table 46 give more detail on the diagnostic registers. see the diagnostics secti on for more detail on the diagnostics available. adc control register the adc control register configure s the core peripherals for use by th e ad7124 - 8 and the mode for the digital interface. the power mode (full power, m i d power, or low power) is selected via this register. also, the mode of operation is selected , for example , c ontinuous conversion or single conversion. the user can also select the standby and power - down modes , as well as any of the calibration modes. in addition, this register contains the clock source select bits and the internal reference enable bits. the reference select bits are contained in the setup configuration registers (see t he adc setups se ction for more information). t he digital interface operation is also selected via the adc control register. this register allows the user to enable the data plus status read and continuous read mode. for more detail s , see the digit al interface section. the details of this register are shown in table 47. table 44 . error register reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x06 error [23: 16] 0 ldo_cap_err adc_cal_err adc_conv_ err adc_sat_ err 0x000000 r [15:8] ainp_ov_ err ainp_uv_ err ainm_ov_ err ainm_uv_ err ref_det _err 0 dldo_psm_ err 0 [7:0] aldo_psm_ err spi_ignore_ err spi_sclk_ cnt_err spi_read_ err spi_write_ err spi_crc_er r mm_crc_ err 0 table 45. e rror enable register reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x07 error _e n [23:16] 0 mclk_cnt_ e n ldo_cap_ chk_test_en ldo_cap_chk adc_cal_ err_en adc_conv_ err_en adc _sat_ err_en 0x000040 rw [15:8] ainp_ov_ err_en ainp_uv_ err_en ainm_ov_ err_en ainm_uv_ e rr_en ref_det _ err_en dldo_psm_ trip_test_en dldo_psm_ err_en aldo_psm_ trip_test_en [7:0] aldo_psm_ err_en spi_ignore_ err_en spi_sclk_ cnt_err_en spi_read_ err_ en spi_write_ err_en spi_crc_ err_en mm_crc_ err_en 0 table 46 . mclk count register reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x08 mclk_c ount [7:0] mclk_count 0x00 r table 47 . adc control register reg . name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x01 adc _control [15:8] 0 dout_ rdy _del cont_read data_status cs _en ref_en 0x 0 000 rw [7:0] power_more mode clk_sel ad7124- 8 data sheet rev. b | page 42 of 91 u nderstanding configuration flexibility in figure 70, figure 71, and figure 72 , the registers shown in black font are program me d for this configuration. the registers shown in gr a y font are redundant. the most straightforward implementation of the ad7124 - 8 is to us e differential inputs with adjacent analog inputs and run all of them with the same setup, gain correction, and offset correction register. for example, the user requires four differential inputs. in this case, the user selects the following differential inputs: ain0/ ain1, ain2/ain3, ain4/ain5, ain6/ain7. programming the gain and offset registers is optional for any use case, as indicated by the dashed lines between the register blocks. if an internal or system offset or full - scale calibration is performed, the gain and offset registers for the selected ch annel are automatically updated. an alternative way to implement these four fully differential inputs is by taking advantage of the eight available setups. motivation fo r this includes having a different speed , noise , or gain requirement on some of the fou r differential inputs vs. other inputs, or there may be a specific offset or gain correction for particular channels. figure 71 shows how each of the differential inputs can use a sepa rate setup, allowing full flex ibility in the configuration of each channel. configur a tion registers channel registers filter registers offset registers gain registers select peripheral functions for adc channel select analog input parts enable the channel select setup 0 select digital filter type and output data rate analog input buffers reference buffers burnout reference source gain sinc 4 sinc 3 sinc 4 + sinc 1 sinc 3 + sinc 1 enhanced 50hz/60hz rejection gain correction optionally programmed per setup as required offset correction optionally programmed per setup as required 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 config_3 config_5 config_6 config_7 config_4 config_0 config_2 config_1 filter_3 filter_5 filter_6 filter_7 filter_4 filter_0 filter_2 filter_1 gain_3 gain_5 gain_6 gain_7 gain_4 gain_0 gain_2 gain_1 offset_3 offset_5 offset_6 offset_7 offset_4 offset_0 offset_2 offset_1 0x09 ch0 0x0a ch1 0x0b ch2 0x0c ch3 0x0d ch4 0x0e ch5 0x0f ch6 0x10 ch7 0x11 ch8 0x12 ch9 0x13 ch10 0x14 ch11 0x15 ch12 0x16 ch13 0x17 ch14 0x18 ch15 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 13048-074 figure 70 . four fully differential inputs, all using a single setup (c onfig _0 , f ilter _0 , g ain _0 , o ffset _0) configur a tion registers filter registers offset registers gain registers select peripheral functions for adc channel select analog input parts enable the channel select setup select digital filter type and output data rate analog input buffers reference buffers burnout reference source gain sinc 4 sinc 3 sinc 4 + sinc 1 sinc 3 + sinc 1 enhanced 50hz/60hz rejection gain correction optionally programmed per setup as required offset correction optionally programmed per setup as required 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 config_ 3 config_5 config_6 config_7 config_4 config_0 config_ 2 config_ 1 filter_3 filter_5 filter_6 filter_7 filter_4 filter_0 filter_2 filter_1 gain_3 gain_5 gain_6 gain_7 gain_4 gain_0 gain_2 gain_1 offset_3 offset_5 offset_6 offset_7 offset_4 offset_0 offset_2 offset_1 0x09 ch0 0x0a ch1 0x0b ch2 0x0c ch3 0x0d ch4 0x0e ch5 0x0f ch6 0x10 ch7 ch8 ch9 ch10 ch11 ch12 ch13 ch14 ch15 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 channel registers 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 13048-075 figure 71 . four fully differentia l inputs with a separate setup p er channel ad7124- 8 data sheet rev. b | page 43 of 91 figure 72 shows an example of how the channel registers span between the analog input pins and the setup configurations downstream. in this random example , two differential inputs and two single - ende d inputs are required. the single - ended inputs are the ain0/ain7 and ain6/ain7 combinations. the first differen - tial input pair (ain0/ain1 ) use s setup 0 . the two single - ended input pairs (ain0/ain7 and ain6/ain7) are set up as diagnostics ; therefore, they use a s eparate setup ( setup 1 ) . the final differential input (ain2/ain3) also uses a separate setup: setup 2. given that three setups are selected for use, the config_ 0, config_ 1, and config_ 2 registers are program med as required, and the filter_ 0, filter _ 1, and filter _ 2 registers are also programmed as required . optional gain and offset correction can be employed on a per setup basis by programming the gain_ 0, gain_ 1, and gain_ 2 registers and the offset_ 0, offset_ 1, and offset_ 2 registers. in the example shown in figure 72 , the channel_ 0 to channel_ 3 re gisters are used. setting the msb (the enable bit) in each of these registers enables the four combinations via the crosspoint multiplexer . when the ad7124 - 8 converts, the sequencer transitions in ascending sequential order from channel_ 0 to channel_ 1 to channel_ 2, and then on to channel_ 3 before looping back to channel_ 0 to repeat the sequence. configur a tion registers filter registers offset registers gain registers select peripheral functions for adc channel select analog input parts enable the channel select setup select digital filter type and output data rate analog input buffers reference buffers burnout reference source gain sinc 4 sinc 3 sinc 4 + sinc 1 sinc 3 + sinc 1 enhanced 50hz/60hz rejection gain correction optionally programmed per setup as required offset correction optionally programmed per setup as required 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 config_3 config_5 config_6 config_7 config_4 config_0 config_ 2 config_ 1 filter_3 filter_5 filter_6 filter_7 filter_4 filter_ 0 filter_ 2 filter_ 1 gain_3 gain_5 gain_6 gain_7 gain_4 gain_0 gain_2 gain_1 offset_3 offset_5 offset_6 offset_7 offset_4 offset_0 offset_2 offset_1 0x09 channel_0 0x0a channel_1 0x0b channel_2 0x0c channel_3 0x0d channel_4 0x0e channel_5 0x0f channel_6 0x10 channel_7 channel_8 channel_9 channel_10 channel_11 channel_12 channel_13 channel_14 channel_15 ain0 ain1 ain2 ain3 ain4 ain5 ain6 ain7 channel registers 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 13048-076 figure 72 . mixed differential and single - ended configuration using multiple shared setups ad7124-8 data sheet rev. b | page 44 of 91 adc circuit information analog input channel the ad7124-8 uses flexible multiplexing; thus, any of the analog input pins, ain0 to ain15, can be selected as a positive input or a negative input. this feature allows the user to perform diagnostics such as checking that pins are connected. it also simplifies printed circuit board (pcb) design. for example, the same pcb can accommodate 2-wire, 3-wire, and 4-wire resistance temperature detectors (rtds). ain0 ain1 av dd av dd av ss av ss av ss av dd av ss a in14 av dd a in15 av dd av ss pga to adc burnout currents 13048-077 figure 73. analog input multiplexer circuit the channels are configured using the ainp[4:0] bits and the ainm[4:0] bits in the channel registers (see table 48). the device can be configured to have 8 differential inputs, 15 pseudo dif- ferential inputs, or a combination of both. when using differential inputs, use adjacent analog input pins to form the input pair. using adjacent pins minimizes any mismatch between the channels. the inputs can be buffered or unbuffered at a gain of 1 but are automatically buffered when the gain exceeds 1. the ainp and ainm buffers are enabled/disabled separately using the ain_bufp and ain_bufm bits in the configuration register (see table 49). in buffered mode, the input channel feeds into a high impedance input stage of the buffer amplifier. therefore, the input can tolerate significant source impedances and is tailored for direct connection to external resistive type sensors such as strain gages or rtds. when the device is operated in unbuffered mode, the device has a higher analog input current. note that this unbuffered input path provides a dynamic load to the driving source. therefore, resistor/capacitor (rc) combinations on the input pins can cause gain errors, depending on the output impedance of the source that is driving the adc input. the absolute input voltage in unbuffered mode (gain = 1) includes the range between av ss ? 50 mv and av dd + 50 mv. the absolute input voltage range in buffered mode at a gain of 1 is restricted to a range between av ss + 100 mv and av dd ? 100 mv. the common-mode voltage must not exceed these limits; otherwise, linearity and noise performance degrade. when the gain is greater than 1, the analog input buffers are automatically enabled. the pga placed in front of the input buffers is rail-to-rail; thus, in this case, the absolute input voltage includes the range from av ss ? 50 mv to av dd + 50 mv. table 48. channel register reg. name bits bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x09 to 0x18 channel_0 to channel_15 [15:8] enable setup 0 ainp[4:3] 0x8001 rw [7:0] ainp[2:0] ainm[4:0] table 49. configuration register reg. name bits bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x19 to 0x20 config_0 to config_7 [15:8] 0 bipolar burnout ref_bufp 0x0860 rw [7:0] ref_bufm ain_bufp ain_bufm ref_sel pga data sheet ad7124- 8 rev. b | page 45 of 91 programma ble gain array (pga) when the gain stage is enabled, the output from the multiplexer is applied to the input of the pga. the presence of the pga means that signals of small amplitude can be gained within the ad7124 - 8 and still maintain excellent noise performance. buf buf analog buffers pga2 pga1 x-mux 24-bit - adc 13048-080 figure 74 . pga the ad7124 - 8 can be programmed to have a gain of 1, 2, 4, 8, 16, 32, 64, or 128 by using the pga bits in the configuration register (see table 49 ). the pga consists of two stages. for a gain of 1, both stages are bypassed. for gains of 2 to 8, a single stage i s used , wh ereas for gains grea ter than 8 , both stages are used . the analog input range is v ref /gain. therefore , with an external 2.5 v reference, the unipolar ranges are from 0 mv to 19.53 mv to 0 v to 2.5 v, and the bipolar ranges are from 19.53 mv to 2.5 v. for high reference val ues, for example, v ref = av dd , the analog input range must be limited. consult the specifications section for more detail s on the se limits. reference the ad7124 - 8 has an embedded 2.5 v reference. the embedded reference is a low noise, low drift reference with 15 ppm/c drift maximum . including the reference on the ad7124 - 8 reduces the number of external co mponents needed in applications such as thermocouple s , leading to a reduced pcb size. band ga p ref 24-bit - adc refin1(+) refout refin1(?) refin2(+) refin2(?) a v dd a v ss a v ss reference buffers 13048-081 figure 75 . reference connections this reference can be used to supply the adc (by setting the ref_en bit in the adc_c ontrol register to 1) or an external reference can be applied. for external references, the adc has a fully differential input capability for the channel. in addition, the user can select one of two external reference options (refin1 or refin2). the refere nce source for the ad7124 - 8 is select ed using the ref_sel bits in the configuration register (see table 49 ). when the internal reference is selected, it is internally connected to the modulator. it can also be made available on the refout pin. a 0.1 f decoupling capacitor is required on refout when the internal reference is active. the common - mode range for the differential reference inputs is fro m av ss ? 50 mv to av dd + 50 mv when the reference buffers are disabled. t he reference inputs can also be buffered on - chip. the buffers require 100 mv of headroom. the reference voltage of refin (refin x (+) ? refin x ( ? )) is 2.5 v nominal, but the ad7124 - 8 is functional with reference voltages fr om 1 v to av dd . in applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the device s, the effect of the low frequency noise in the excitation source is removed, because the application is ratiometric . if the ad7124 - 8 is used in nonratiometric applications, use a low noise re ference. the r ecommended 2.5 v reference voltage sources for the ad7124 - 8 include the adr4525 , which is a low noise, low power r eference . n ote that the reference input provides a high impedance, dynamic load when unbuffered . because the input impedance of each reference input is dynamic, resistor/capacitor combination s on these inputs can cause dc gain errors if the reference input s are unbuffered , depending on the output impedance of the source driving the reference inputs. reference voltage sources typically have low output impedances and are, therefore, tolerant to having decoupling capacitors on refin x (+) without introducing gai n errors in the system. deriving t he reference input voltage across an external resistor means that t he reference input sees a significant external source impedance. in this situation, using the reference buffers is required. refinx(+) 1f 4.7f adr4525 2.5v ref refinx(?) 0.1f 4.7f 3v 13048-082 figure 76 . adr4525 to ad7124 - 8 connections ad7124- 8 data sheet rev. b | page 46 of 91 bipolar/unipolar con figuration the analog input to the ad7124 - 8 can accept either unipolar or bipolar input voltage ranges , which allows the user to tune the adc input range to the sensor output range. when a split power supply is used, the device accepts truly bipolar inputs. when a single power supply is used, a bipolar input range does not imply that the device can tolerate negative voltages with respect to system av ss . unipolar and bipolar signals on the ain p input are referenced to the voltage on the ain m input. for exampl e, if ain m is 1.5 v and the adc is configured for unipolar mode with a gain of 1, the input voltage range on the ain p input is 1 .5 v to 3 v when v ref = av dd = 3 v . if the adc is configured for bipolar mode, the analog input range on the ain p input is 0 v t o av dd . the bipolar/unipolar option is chosen by programming the bipolar bit in the configuration register. data output coding when the adc is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input v oltage resulting in a code of 00 00, a mi d scale voltage resulting in a code of 100 000, and a full - scale input voltage resulting in a code of 111 111. the output code for any analog input voltage can be represented as code = (2 n a in g ain )/ v ref w hen the adc is configured for bipolar operation, the output code is offset binary with a negative full - scale voltage resulting in a code of 000 000, a zero differential input voltage resulting in a code of 100 000, and a positive full - scale input volta ge resulting in a code of 111 111. the output code for any analog input voltage can be represented as code = 2 n ? 1 [( a in g ain / v ref ) + 1] where: n = 24. a in is the analog input voltage. g ain is the gain setting (1 to 128). excitation currents the ad7124 - 8 also contains two matched, software configu rable, c onstant current sources that can be programmed to equal 50 a, 100 a, 250 a, 500 a, 750 a , or 1 ma. these current sources can be used to excite external resistive bridge s or rtd sensors. both current sources source currents from av dd an d can be directed to any of the analog input pins (see figure 77 ). the pins on which the currents are made available are programmed using the iout1_ch and iout0_ch bits in the io_c ontrol _1 register (see table 50 ). the magnitude of each current source is individually programmable using the iout1 and iout0 bits in the io_c ontrol _1 register. in addition, b oth currents can be outp ut to the same analog input pin . note that the on - chip reference does n ot need to be enabled when using the excitation currents. ain0 ain1 av dd vbias iout1 iout0 av dd av ss av ss av dd av ss ain15 av dd av ss vbias vbias pga to adc burnout currents 13048-083 figure 77 . excitation current and bias voltage connections bridge power - down switch in bridge applications such as strain gauges and load cells, the bridge itself consumes the majority of the current in the system. for example, a 350 load cell requires 8.6 ma o f current when excited with a 3 v supply. to minimize the current consumption of the system, the bridge can be disconnected (when it is not being used) using the br idge power - down switch. the switch can withstand 30 ma of continuous current, and it has an on r esistance of 10 maximum. the pd sw bit in the io_c ontrol _1 register controls the switch. table 50. i nput/output control 1 register re g. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x03 io_ control_ 1 [23:16] gpio_dat4 gpio_dat3 gpio_dat2 gpio_dat1 gpio_ctrl4 gpio_ctrl3 gpio_ctrl2 gpio_ctrl1 0x000000 rw [15:8] pdsw 0 iout1 iout0 [7:0] iout1_ch iout0_ch data sheet ad7124- 8 rev. b | page 47 of 91 logic outputs the ad7124 - 8 has four general - purpose digital outputs: p 1 to p 4 . these are enabled using the gpio_ctrl bits in the io_c ontrol _1 register (see table 5 0 ). the pins can be pulled high or low using the gpio_d at x bits in the register; that is, the value at the pin is determined by t he setting of the gpio_dat x bits. the logic levels for these pins are determined by av dd rather than by io v dd . when the io_c on trol _1 register is read, the gpio_dat x b it s reflect the actual value at the pins; this is useful for short - circuit detection. these pins can be used to drive external circuitry, for example, an external multiplexer. if an external multiplexer is used to i ncrease the channel count, the multiplexer logic pins can be controlled via the ad7124 - 8 general - purpose output pins. the general - purpose output pins can be used to select the active multiplex er pin. because the operation of the multiplexer is independent of the ad7124 - 8 , reset the modulator and f ilter using the sync pin or by writing to the mode or configura tion register each time that the multiplexer channel is changed. bias voltage generat or a bias voltage generator is included on the ad7124 - 8 (see figu re 77 ). it biases the negative terminal of the selected input channel to ( av dd ? av ss )/2. this function is useful in thermocou - ple a pplica tions, as the voltage generated by the thermocouple must be biased around some dc voltage if the adc operates from a single power supply. the bias vol tage generator is controlled u sing the vbias x b its in the io_c ontrol _2 register (see table 52 ) . the power - up time of the bias voltage generator is dependent on the load capacitance. consult the specifications section for more detail s. clock the ad7124 - 8 includes an internal 614.4 khz clock on chip. this internal clock has a tolerance of 5 %. use e ither the internal clock or an external clock as the clock source to the ad7124 - 8 . the clock source is selected using the clk_sel bits in the adc_ c ontrol register (see table 53). the internal clock can also be made available at the clk pin. this is useful when several adcs are used in an application and the devices must be synchronized. the internal clock from one device can be used as the clock source for all adcs in the system. using a common clock, the devices can be synchron ized by applying a common reset to all devices, or the sync pin can be pulsed. power m odes the ad7124 - 8 has three power modes: full power mode, mid power mode, and low power mode. the mode is selected using the power_mode bits in the adc_control register. the power mode affects the power consumption of the device as well as changing the master clock frequency. a 614.4 khz clock is used by the device. however, this clock is internally divided, the division factor being dependent on the power mode. thus , the range of output data rates and performance is affected by the power mode. table 51. power modes power mode master clock (khz) output data rate 1 (sps ) current full power 614.4 9.37 to 19,200 see the specifications section mid power 153.6 2.34 to 4800 low power 76.8 1.17 to 2400 1 unsettled, using a sinc 3 /sinc 4 filter. table 52. i nput/ o utput control 2 register reg. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x04 io_control_2 vbias15 vbias14 vbias13 vbias12 vbias11 vbias10 vbias9 vbias8 0x0000 rw vbias7 vbias6 vbias5 vbias4 vbias3 vbias2 vbias1 vbias0 table 53 . adc control register reg. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x01 adc_control 0 dout_ rdy _del cont_read data_status cs _en ref_en 0x0000 rw pow er_mode mode clk_sel ad7124- 8 data sheet rev. b | page 48 of 91 standby and power - down modes in standby mode, most blocks are powered down. the ldos remain active so that registers maintain their contents. if enabled, the reference, internal oscillator, digital outputs p1 to p4, the bia s voltage generator , and the low - side power switch remain active. these blocks can be disabled also, if required, by setting the corresponding bits appropriately. the excitation currents, reference detect ion , and ldo capacitor detect ion functions are disab led in standby mode. other diagnostics remain active if enabled when the adc is in standby mode. diagnostics can be enabled or disabled while in standby mode. however, any diagnostics that require the master clock ( undervoltage/overvoltage detection, ldo trip tests, memory map crc , and mclk counter) must be enabled when the adc is in continuous conv ersion mode or idle mode ; these diagnostics do not function if enabled in standby mode. the standby current is typically 15 a when the ldos only are enabled. if functions such as the bias voltage generator remain active in standby mode, the current increases by 36 a typically. if the internal oscillator remains active in standby mode, the current increases by 22 a typically. when exiting standby mode, the ad7124 - 8 requires 130 mclk cycles to power up and settle . in power - down mode, all blocks are powered down, including the ldos. all registers lose t heir contents, and the digital outputs p1 to p 4 are placed in tristate. to prevent accidental entry to power - down mode, the adc must first be placed into standby mode. exiting power - down mode requires 64 sclk cycle s with cs = 0 and din = 1, that is, a serial interface reset. the ad7124 - 8 requires 2 ms typically to power up and settle . the por_flag in the status register can be monit or ed to determine the end of the power up/settling period. after this time, the user can access the on - chip registers. the power - down current is 2 a typically. digital interface t he programmable functions of the ad7124 - 8 are controlled using a set of on - chip registers. data is written to these registers via the serial interface. read access to the on - chip registers is also provided by this interface. all communications with the device must start with a write to the communications register. after power - on or reset, the device exp ects a write to its communications register. the data written to this register determines whether the next operation is a read operation or a write operation, and determines to which register this read or write operation occurs. therefore, write access to any of the other registers on the device s begins with a write operation to the communications register, followed by a write to the selected register. a read operation from any other register (except when continuous read mode is selected) starts with a writ e to the communications register, followed by a read operation from the selected register. the serial interface of the ad7124 - 8 consists of four signals: cs , din, sclk , and dout/ rdy . the din line transfer s data into the on - chip registers, wh ereas dout/ rdy access es data from the on - chip registers. sclk is the serial clock input for the device, and all data transfers (either o n din or dout/ rdy ) occur with respect to the sclk signal. the dout/ rdy pin also operates as a data ready signal; the line goes low when a new data - word is available in the output register. it is reset high when a read operation from the data register is complete. it also goes high before the data register updates to indicate when not to read from the device, to ensure that a data read is not attempted while the register is being updated. cs is used to select a device. it can decode the ad7124 - 8 in systems where several components are connected to the serial bus. figure 3 and figure 4 show timing diagrams for interfacing to the ad7124 - 8 with cs decoding the device s. figure 3 shows the timing for a r ead operation from the output shift register of the ad7124 - 8 . figure 4 shows the timing for a write operatio n to the input shift register. a delay is required between consecutive spi communications. figure 5 shows the delay required between spi r ead/write operations. i t is possible to read the same word from the data register several times, even though the dout/ rdy line r eturns high after the first read operation. however, care must be taken to ensure that the read operations are complete before the next output update occurs. in continuous read mode, the data register can be read only once. the serial interface can operat e in 3 - wire mode by tying cs low. in this case, the sclk, din, and dout/ rdy lines communicate with the ad7124 - 8 . the end of the conversion can be monitored using the rdy bit in the status register. this scheme is su itable for interfacing to micro controllers. if cs is required as a decoding s ignal, it can be generated from a port pin. for microcontroller interfaces, it is recommended that sclk idle high between data transfers. the ad7124 - 8 can be operated with cs being used as a frame synchronization signal. this scheme is useful for dsp interfaces. in this case, the first bit (msb) is effectively clocked out by cs , because cs normally occurs after the falling edge of sclk in dsps. sclk can continue to run between data transf ers, provided the timing numbers are obeyed. cs must be used to frame read and write operations and the cs _en bit in the adc_c ontrol register must be set when the diagnostics spi_read_err, spi_write_err , or s pi_sclk_cnt_err are enabled. the serial interface can be reset by writing a series of 1s on the din input. see the reset sect i on for more detail s. reset returns the interface to the state in which it is expecting a write to the co mmunications register the ad7124 - 8 can be configured to continuously convert or perform a single conversion (see figure 78 through figure 80). data sheet ad7124- 8 rev. b | page 49 of 91 single conversion mode in single co nversion mod e, the ad7124 - 8 performs a single conversion and is placed in standby mode after the conversion is complete. the ad7124 - 8 requires 130 mclk cycles to exit standby mode. if a master clock is present (external master clock o r the internal oscillator is enabled), dout/ rdy goes low to indicate the completion of a conversion . when the data - word is read from the data register, dout/ rdy goes high. the data register can be read several times, if required, even when dout/ rdy is hig h. if several channels are enabled, the adc automatically sequences through the enabled channels and performs a conversion on each channel. when a conversion is started, dout/ rdy goes high and remains high until a valid conversion is available and cs i s low. as soon as the conversion is available, dout/ rdy goes low. the adc then selects the next channel and begins a conversion. the user can read the present conversion whi le the next conversion is being performed. as soon as the next conversion is complete, the data register is updated; therefore, the user has a limited period in which to read the conversion. when the adc has performed a single conversion on each of the selected channels, it retu rns to idle mode. if the dat a _sta tus bit in the adc_c ontrol register is set to 1, the contents of the status register are output along with the conversion each time that the data read is performed. the four lsbs of the status register indicate the channel to which the conversion corresponds . continuous conversion mode continuous conversion is the default power - up mode. the ad7124 - 8 converts continuously, and the rdy bit in the status register goes low each time a conversion is complete. if cs is low, the dout/ rdy line also goes low when a conversion is complete. to read a conversion, wri te to the communications register, indic ating that the next operation is a read of the data register. when the data - word is read from the data register, dout/ rdy goes high. the user can read this register additional times, if required. however, the user must ensure that th e data register is not being accessed at the completion of the next con version; otherwise the new conversion word is lost. when several channels are enabled, the adc automatically sequences through the enabled channels, performing one conversion on each c hannel. when all channels are converted, the sequence starts again with the first channel. the channels are converted in order from lowest enabled channel to highest enabled channel. the data register is updated as soon as each conversion is available. the dout/ rdy pin pulses low each time a conversion is available. the user can then read the c onversion while the adc converts the next enabled channel . if the data_stat us bit in the adc_control register is set to 1, the contents of the status register, along with the conversion data, are output each time the data register is read. the status register indicates the channel to which the conversion corresponds. din sclk dout/rdy cs 0x01 0x0004 0x42 d at a 13048-087 figure 78 . single conversion configuration din sclk dout/rdy cs 0x42 0x42 d at a d at a 13048-088 figur e 79 . continuous conversion configuration ad7124- 8 data sheet rev. b | page 50 of 91 din sclk dout/rdy cs dat a dat a 0x01 0x0800 13048-089 figure 80 . continuous read configuration continuous read mode in continuous read mode, it is not required to write to the communications register before reading adc data; apply the required number of sclks after dout/ rdy goes low to indicate the end of a conversion. when the conversion is read, dout/ rdy returns high until the next conversion is available. in this mode , the data can be read only once. e nsure that the data - word is read before the next conversion is complete. if the user has not read the conversion before the completion of the next conversion , or if insufficient serial clocks are applied to the ad7124 - 8 to read the word, the serial output register is reset when the next conversion is complete, and the new conversion is placed in the output serial register. the adc must be configured for contin uous conversion mode to use continuous read mode. to enable continuous read mode, set the con t_ read bit in the adc_ control register. when this bit is set, the only serial interface operations possible are reads from the data register. to exit con tinuous r ead mode, issue a dummy read of the adc data register command (0x4 2 ) while rdy is low. alternatively, apply a software reset, that is, 64 sclks with cs = 0 and din = 1. this resets the adc and all register cont ents. these are the only commands that the interface recognizes after it is placed in continuous read mode. din must be held low in continuous read mode until an instruction is to be written to the device. if multiple adc channels are enabled, each channe l is output in turn, with the status bits being appended to the data if data_ status is set in the adc_ control register. the status register indicates the channel to which the conversion corresponds. d ata_s tatus the contents of the status regis ter can be a ppended to each con version on t he ad7124 - 8 . this is a useful function if several channels are enabled. each time a conversion is output, the contents of the status register are appended. the f our lsbs of the status register indicate to which channel the conversion corresponds. in addition, the user can determine if any errors are being flagged via the error_flag bit. to append the status register contents to every conversion, the data_status bi t in the adc_c ontrol register is set to 1. serial interface reset (dou t_ rdy _ del and cs _en bits) the instant at which the dout/ rdy pin changes from being a dout pin to a rdy pin is pro grammable on the ad7124 - 8 . by default, the dout/ rdy pin changes functionality after a period of time following the last sclk rising edge, the sclk edge on which the lsb is re ad by the processor. this time is 10 ns minimum by default and, by setting the dout_ rdy _del bit in the adc_ control register to 1, can be extended to 1 10 ns mini mum . by setting the cs _en bit in the adc_ control register to 1, the change of functionality is controlled by the cs rising edge. in this case, the dout/ rdy pin continues to output the lsb of the register being read until cs is taken high. only on the cs rising edge does the pin change from a dout pin to a rdy pin. this configuration is useful if the cs signal is used to frame all read operations. if cs is not used to frame all read operatio ns, set cs _en to 0 so that dout/ rdy changes functionality following the last sclk edge in the read operation. cs _en must be set to 1 and the cs signal must be used to frame all read an d write operations when the spi_read_err, spi_write_err , and spi_sclk_cnt_err diagnostic functions are enabled. the serial interface is always reset on the cs rising edge , that is , the interface is reset to a known state whereby it awaits a write to the communications register. therefore, if a read or write operation is performed by performing multiple 8 - bit data transfers, cs must be held low until the all bits are transferred. reset the circuitry and serial interface of the ad7124 - 8 can be reset by writing 64 consecutive 1s to the device. this resets the logic, the digital filter, and the analog modulator, and all on - chip registers are reset to their defau lt values. a reset is automatically performed on power - up. a reset requires a time of 90 mclk cycles . the por_flag bit in the status register is set to 1 when the reset is initiated and the n is set to 0 when the reset is complete . a reset is useful if the serial interface becomes asynchronous due to noise on the sclk line. data sheet ad7124- 8 rev. b | page 51 of 91 calibration the ad7124 - 8 provides four calibration modes that can be used to eliminate the offset and gain errors on a per setup basis: ? internal zero - scale calibration mode ? internal full - scale calibration mode ? system zero - scale calibration mode ? system full - scale calibration mode only one channel can be active during calibration. after each conversion, the adc conversion resul t is scaled using the adc calibratio n registers before being written to the data register. the default value of the offset register is 0x800000, and the nominal value of the gain register is 0x5xxxxx . the calibration range of the adc gain is from 0.4 v r ef / g ain to 1.05 v ref / g ain. the following equations show the calculations that are used in each calibration mode . in unipolar mode, the ideal relationship that is, not taking into account the adc gain error and offset error is as follows: 2 0x400000 ) 0x800000 ( 2 75 . 0 23 ? ? ? ? ? ? ? ? ? ? = gain offset v v data ref in in bipolar mode, the ideal relationship ? that is, not taking into account the adc gain error and offset error ? is as follows: 0x800000 0x400000 0x800000) ( 2 0.75 23 + ? ? ? ? ? ? ? ? ? ? = gain offset v v data ref in to start a calibration, write the relevant value to the m ode bits in the adc_c ontrol register. the dout/ rdy pin and the rdy bit in the status register go high when the calibration initiates. when the calibration is complete, the contents of the corresponding offset or gain register are updated, the rdy bit in the status register is reset, the dout/ rdy pin returns low (if cs is low), and the ad7124 - 8 reverts to idle mode. during an internal o ff set calibration, the selected positive analog input pin is disconnected, and it is connected internally to the selected negative analog input pin. for this reason, it is necessary to ensure that the voltage on the selected negative analog input pin does no t exceed the allowed limits and is free from excessive noise and interference. to perform an internal full - scale calibration, a full - scale input voltage is automatically connected to the selected analog in put for this calibration. a full - scale calibration is recommended each time the gain of a channel is changed to minimize the full - scale error. when performing internal calibrations, the internal full - scale calibration must be performed before the internal zero - scale calibration. therefore, write the value 0x800000 to the offset register before performing the internal full - scale calibration, which ensures that the offset register is at its default value. system calibrations expect the system zero - scale (offset) and system full - scale (gain) voltages to be app lied to the adc pins before initiating the calibration modes. as a result, errors external to the adc are removed. the system zero - scale calibration must be performed before the system full - scale calibrati on . from an operational point of view, treat a cali bration like another adc conversion. set the system software to monitor the rdy bit in the status register or the dout/ rdy pin to determine the end of a calibration via a polling sequence or an interrupt - driven rout ine. an internal/system offset calibration and system full - scale calibration require s a time equal to the settling time of the select ed filter t o be completed. the internal full - scale calibration requires a time equal to one settling period for a gain of 1 and a time of four settling periods for gains greater than 1. a calibration can be performed at any output data rate. using lower output data rates results in better calibration accuracy and is accurate for all output data rates. a new calibration is req uired for a given channel if the reference source or the gain for that channel is changed. offset and system full - scale calibrations can be performed in any power mode. internal full - scale calibrations can be performed in the low power or mid power modes only. thus , when using full power mode, the user must select mid or low power mode to perform the internal full - scale calibration. however, an interna l full - scale calibration performed in low or mid power mode is valid in full power mode, if th e same gain is used. the offset error is typically 15 v for gains of 1 to 8 and 200/gain v for higher output data rates. an internal or system o ffset calibration reduces the offset error to the order of the noise. the gain error is factory calibrated at ambient te mperature and at a gain of 1 . following this calibrat ion, the gain error is 0.00 2 5 % maximum . therefore, internal full - scale calibrations at a gain of 1 are not supported on the ad7124 - 8 . for other gains, the gain error is 0.3%. an internal full - scale calibration at ambient temperature reduces the gain error to 0.0 16 % maximum for gains of 2 to 8 and 0.025% typically for higher gains. a system full - scale calibration reduces the gain error to the order of the noise. the ad7124 - 8 provides the user with access to the on - chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and to write its own calibration coeffi cients from prestored values in the eeprom . a read or write of the offset and gain registers can be performed at any time except during an internal or self - calibration. the values in the calibration registers are 24 bits wide. the span and offset of the de vice can also be manipulated using the registers. ad7124- 8 data sheet rev. b | page 52 of 91 span and offset limi ts whenever a system calibration mode is used, the amount of offset and span that can be accommodated is limited . the overriding requirement in determining the amount of offset and gain that can be accommodated by the device is the requirement that the positive full - scale calibration limit is 1.05 v ref / g ain . this allows the input range to go 5% above the nominal range. the built - in headroom in the ad7124 - 8 analog modulator ensures that the device still operate s correctly with a positive full - scale voltage, which is 5% beyond the nominal. the range of input span in both the unipolar and bipolar modes has a minimum valu e of 0.8 v ref / g ain and a maximum value of 2.1 v ref / g ain. however, the span , which is the difference between th e bottom of the ad7124 - 8 input range and the top of its input range , must account for the limitation on the positive full - scale voltage. the amount of offset that can be accommodated depends o n whether the unipolar or bipolar mode is being used. t he offset must account for the limitation on the positive full - scale voltage. in unipolar mode, there is considerable flexibility in handling negative (with respect to ain m ) offsets. in both unipolar a nd bipolar modes, the range of positive offsets that can be handled by the device depends on the selected span. therefore, in determining the limits for system zero - scale and full - scale calibrations, the user must ensure that the offset range plus the span range does exceed 1.05 v ref / g ain . this is best illustrated by looking at a few examples. if the device is used in unipolar mode with a required span of 0.8 v ref / g ain , the offset range that the system calibration can handle is from ? 1.05 v ref / g ain to +0.25 v ref / g ain . if the device is used in unipolar mode with a required span of v ref / g ain , the offset range t hat t he system calibration can handle is from ? 1.05 v ref / g ain to +0.05 v ref / g ain . similarly, if the device is used in unipolar mode and requ ired to remove an offset of 0.2 v ref / g ain , the span range that the system calibration can handle is 0.85 v ref / g ain . if the device is used in bipolar mode with a required span of 0.4 v ref / g ain , then the offset range that the system calibration can han dle is from ? 0.65 v ref / g ain to +0.65 v ref / g ain . if the device is used in bipolar mode with a required span of v ref / g ain , the offset range the system calibration can handle is from ? 0.05 v ref / g ain to +0.05 v ref / g ain . similarly, if the device is used in bipolar mode and required to remove an offset of 0.2 v ref / g ain , the span range that the system calibration can handle is 0.85 v ref / g ain . system synchroni z ation the sync input allows the user to reset the modulator and the digital filt er without affecting any of the setup conditions on the device . this allows the user to start gathering samples of the analog input from a known point in time, that is, the rising edge of sync . take sync low fo r at least four master clock cycles to implement the synchronization function. if multiple ad7124 - 8 devices are operated from a common master clock, they can be synchronized so that their dat a registers are updated simultaneously. a falling edge on the sync pin resets the digital filter and the analog modulator and places the ad7124 - 8 into a consistent, know n state. while the sync pin is low, the ad7124 - 8 is maintained in this state. on the sync rising edge, the modulator and filter e x it this reset st ate and, on the next clock edge, the device starts to gather input samples again. in a system using multiple ad7124 - 8 devices, a common signal to the ir sync pins synchro nizes their opera tion. this is normally performed after each ad7124 - 8 has performed its own calibration or has calibration coefficients loaded into its calibration registers. the conversions f rom the ad7124 - 8 devices are then synchronized. the device exits reset on the master clock falling edge following the sync low to high transition. therefore, when multip le devices are being syn chronized, pull the sync pin high on the master clock rising edge to ensure that all devices begin sampling on the master clock falling edge. if the sync pin is not taken high in suffici ent time, it is possible to have a difference of one master clock cycle between the devices; that is, the instant at which conversions are available differs from device to device by a maximum of one master clock cycle. the sync pin c an also be used as a start conversion command. in this mode, the rising edge of sync starts conversion and the falling edge of rdy indicates when the conversion is complete. the settling time of the filter must be allowed for each data register update. for example, if the adc is conf igured to use the sinc 4 filter and zero latency i s disabled , the settling time equals 4/f adc where f adc is the output data rate when continuously converting on a single channel. data sheet ad7124- 8 rev. b | page 53 of 91 digital fi lter table 54 . filter register s reg. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x21 to 0x28 filter_0 to filter_7 filter rej60 post_filter single_cycle 0x060180 rw 0 fs[10:8] fs[7:0] the ad7124 - 8 offers a great deal of flexibility in the digital filter. the device has several filter options. the option selected affects the output data rate, settling time, and 50 hz and 60 hz rejection. the following sections describe each filter type, indicating the available output data rates for each filter option. the filter response along with the settling time and 50 hz and 60 hz rejection is also discussed. the filter bits in the filt er register select between the sinc type filter. sinc 4 filter when the ad7124 - 8 is powered up, the sinc 4 f ilter is selected by default. this filter gives excellen t noise performance over the complete range of output data rates. it also gives the best 50 hz/ 60 hz rejection, but it has a long settling time. in figure 81 , the b locks shown in gray are unused. s i n c 3 / s i n c 4 f i l t e r m o d u l a t o r a v e r a g i n g b l o c k p o s t f i l t e r 13048-091 figure 81 . sinc 4 fi lter sinc 4 output data rate/settling time the output data rate (the rate at which conversions are available on a single channel when the adc is continuously converting) is equal to f adc = f clk /(32 fs[10:0] ) where: f adc is the output data rate. f clk is the master clock frequency (614.4 khz in full power mode, 153.6 khz in mid power mode , and 76.8 khz in low power mode). fs[10:0] is the decimal equivalent of the fs[10:0] bits in the f ilter register. fs[10:0] can have a value from 1 to 2047. the output d ata rate can be programmed from ? 9.38 sps to 19,200 sps for full power mode ? 2.35 sps to 4800 sps for mid power mode ? 1.17 sps to 2400 sps for low power mode the settling time for th e sinc 4 filter is equal to t settle = ( 4 32 fs[10:0] + dead t ime )/ f clk w here dead t ime = 60 when fs[10:0] = 1 and 94 when fs[10:0] > 1 when a channel change occurs, the modulator and filter are reset. the settling time is allow ed to generate the first conver sion after the channel change. subsequent conversions on this channel occur at 1 /f adc . conversions channe l a channe l channe l b ch a ch a ch a ch b ch b ch b 1/f adc dt/ f clk notes 1. dt = dead time. 13048-092 figure 82 . sinc 4 channel change when conversions are performed on a single channel and a step change occurs, the adc does not detect the change in the analog input. therefore, it continues to output conversions at the programmed output data rate. however, it is at least four conversions later before the output data accurately reflect s the analog input. if the step change occurs while the adc is processing a conversion, then the adc takes five conversions after the step change to generate a fully settled result. ana l o g i n p u t ad c o u t p u t f u ll y se ttl ed 1/ f adc 13048-093 figure 83 . asynchronous step change in the analog input the 3 db frequency for the sinc 4 filter is equal to f 3db = 0.23 f adc table 55 gives some exa mples of the relationship between the values in the fs[ 10 :0] bits and the corresponding output data rate and settling time. table 55 . examples of output data rates and the corresponding settling time s for the sinc 4 filter power mode fs [ 10 :0] output data rate (sps) settling time (ms) full power (f clk = 614.4 khz) 192 0 10 400 .15 384 50 80 .15 320 60 66. 82 mid power (f clk = 153.6 khz) 480 10 400 .61 96 50 80 .61 80 60 6 7 . 28 low power (f clk = 76.8 khz) 240 10 40 1.22 48 50 8 1. 22 40 60 67.89 ad7124-8 data sheet rev. b | page 54 of 91 sinc 4 zero latency zero latency is enabled by setting the single_cycle bit in the filter register to 1. with zero latency, the conversion time when continuously converting on a single channel approximately equals the settling time. the benefit of this mode is that a similar period of time elapses between all conversions irrespective of whether the conversions occur on one channel or whether several channels are used. when the analog input is continuously sampled on a single channel, the output data rate equals f adc = f clk /(4 32 fs[10:0] ) where: f adc is the output data rate. f clk is the master clock frequency. fs[10:0] is the decimal equivalent of the fs[10:0] bits in the setup filter register. when the user selects another channel, there is an extra delay in the first conversion of dead time / f clk where dead time = 60 when fs[10:0] = 1 and 94 when fs[10:0] > 1. at low output data rates, this extra delay has little impact on the value of the settling time. however, at high output data rates, the delay must be considered. table 56 summarizes the output data rate when continuously converting on a single channel and the settling time when switching between channels for a sample of fs[10:0] values. when switching between channels, the ad7124-8 allows the complete settling time to generate the first conversion after the channel change. therefore, the adc automatically operates in zero latency mode when several channels are enabledsetting the single_cycle bit has no benefits. table 56. examples of output data rates and the corresponding settling times for the sinc 4 filter (zero latency) power mode fs[10:0] output data rate (sps) settling time (ms) full power (f clk = 614.4 khz) 1920 2.5 400.15 384 12.5 80.15 320 15 66.82 mid power (f clk = 153.6 khz) 480 2.5 400.61 96 12.5 80.61 80 15 67.28 low power (f clk = 76.8 khz) 240 2.5 401.22 48 12.5 81.22 40 15 67.89 when the analog input is constant or a channel change occurs, valid conversions are available at a near constant output data rate. when conversions are being performed on a single channel and a step change occurs on the analog input, the adc continues to output fully settled conversions if the step change is synchronized with the conversion process. if the step change is asynchronous, one conversion is output from the adc, which is not completely settled (see figure 84). a nalog input adc output fully settled 1/ f adc 13048-094 figure 84. sinc 4 zero latency operation sequencer the description in the sinc 4 filter section is valid when manually switching channels, for example, writing to the device to change channels. when multiple channels are enabled, the on-chip sequencer is automatically used; the device automatically sequences between all enabled channels. in this case, the first conversion takes the complete settling time as listed in table 55. for all subsequent conversions, the time needed for each conversion is the settling time also, but the dead time is reduced to 30. sinc 4 50 hz and 60 hz rejection figure 85 shows the frequency response of the sinc 4 filter when the output data rate is programmed to 50 sps and zero latency is disabled. for the same configuration but with zero latency enabled, the filter response remains the same but the output data rate is 12.5 sps. the sinc 4 filter provides 50 hz (1 hz) rejection in excess of 120 db minimum, assuming a stable master clock. ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 2 5 5 0 7 5 1 0 0 1 2 5 1 5 0 f r e q u e n c y ( h z ) filter gain (db) 13048-095 figure 85. sinc 4 filter response (50 sps output data rate, zero latency disabled or 12.5 sps output da ta rate, zero latency enabled) data sheet ad7124- 8 rev. b | page 55 of 91 figure 86 shows the frequency response of the sinc 4 filter when the output data rate is programmed to 60 sps and zero latency is disabled. for the same configuration but with zero latency enabled , the filter response remains the same but the out put data rate is 15 sps . the sinc 4 filter provides 60 hz (1 hz) rejection of 120 db minimum , assuming a stable master clock. ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequenc y (hz) fi l ter gain (db) 13048-096 figure 86 . sinc 4 filter response ( 60 sps output data r ate, zero latency disabled or 15 sps output data rate, zero latency enabled ) when t h e output data rate is 10 sps with zero latency disabled or 2.5 sps with zero latency enabled , simultaneous 50 hz and 60 hz rejection is obtained . the sinc 4 filter provides 50 hz (1 hz) and 60 hz (1 hz) rejection of 120 db minimum , assuming a stable master clock. ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequenc y (hz) fi l ter gain (db) 13048-097 figure 87 . sinc 4 filter response ( 10 sps output data r ate, zero latency disabled or 2.5 sps output data rate, zero latency enabled ) simultaneous 50 hz/60 hz rejection can also be achiev ed using the rej60 bit in the f ilter register. when the sinc filter places a notch a 50 hz, the rej60 bit places a first order notch at 60 hz. the output data rate is 50 sps when zero latency is disabled and 12.5 sps when zero latency is enabled. figure 88 shows the frequency response of the sinc 4 filter. the filter provides 50 hz 1 hz and 60 hz 1 hz rejection of 8 2 db minimum, assuming a stable master clock. ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 25 50 75 100 125 150 frequenc y (hz) fi l ter gain (db) 13048-098 figure 88 . sinc 4 filter response ( 50 sps o utput data r ate, zero latency disabled or 12.5 sps output data rate, zero latency enabled , rej60 = 1) sinc 3 filter a sinc 3 filter can be used instead of the sinc 4 filter. the filter is selected using the filter bit s in the filter register. this fil ter has good noise perform ance , moderate settling time , and moderate 50 hz and 60 hz (1 hz) rejection. in figure 89 , the blocks shown in gray are unused . s i n c 3 / s i n c 4 f i l t e r m o d u l a t o r a v e r a g i n g b l o c k p o s t f i l t e r 13048-099 figure 89 . sinc 3 filter sinc 3 output dat a rate and settling time the output data rate (the rate at which conversions are available on a single channel when the adc is continuously converting) equals f adc = f clk /( 32 fs[ 10 :0]) where: f adc i s the output data rate. f clk is the master clock freque ncy (614.4 khz in full power mod e, 153.6 khz in mid power mode a nd 76.8 khz in low power mode). fs[10:0] is the decimal equivalent of the fs[10:0] bits in the f ilter register. fs[10:0] can have a value from 1 to 2047. the output data rate can be programme d from ? 9.38 sps to 19,200 sps for full power mode ? 2.35 sps to 4800 sps for mid power mode ? 1.17 sps to 2400 sps for low power mode the settling time for the sinc 3 fi lter is equal to t settle = ( 3 32 fs[ 10 :0] + dead t ime )/ f clk where dead t ime = 60 when fs[10:0] = 1 and 94 fs[10:0] >1. the 3 db frequency is equal to f 3db = 0.272 f adc ad7124- 8 data sheet rev. b | page 56 of 91 table 57 gives some examples of fs [10:0] settings and the corresponding output data rates and settling times. table 57 . examples of output data rates and the corresponding settling time s for the sinc 3 filter power mode fs[ 10 :0] output data rate (sps) settling time (ms) full power (f clk = 614.4 khz) 1920 10 300.15 384 50 60.15 320 60 50.15 mid power (f clk = 153.6 k hz) 480 10 3 00 .61 96 50 6 0 .61 80 60 50.61 low power (f clk = 76.8 khz) 240 10 3 0 1.22 48 50 61.22 40 60 51.22 when a channel change occurs, the modulator and filter are reset. the complete settling time is allowed to generate the first conversion a fter the channel change (see figure 90 ). subsequent conversions on this channel are available at 1/f adc . channe l a channe l channe l b conversions ch a ch b ch a ch b 1/f adc dt/ f clk 13048-100 notes 1. dt = dead time. figure 90 . sinc 3 channel change when conversions are performed on a single channel and a step cha nge occurs, the adc does not detect the change in the analog input. therefore, it continues to output conversions at the programmed o utput data rate. however, it is at least three conversions later before the output data accurately reflects the analog inpu t. if the step change occurs while the adc is processing a conversion, the adc takes four conversions after the step change to generate a fully settled result. 1/ f adc analog input adc output fully settled 13048-101 figure 91 . asynchronous step change in the analog input sinc 3 zero la tency zero latency is enabled by setting the single_cycle bit in the f ilter register to 1. with zero latency, the conversion time when continuously converting on a single channel approximately equals the settling time. the benefit of this mode is that a si milar period of time elapses between all conversions irrespective of whether the conversions occur on one channel or whether several channels are used. when the analog input is continuous ly sampled on a single channel, t he output data rate equals f adc = f clk /( 3 32 fs[ 10 :0]) where: f adc is the output data rate. f clk is the master clock frequency . fs[ 10 :0] is the decimal equivalent of the fs [10:0] bits in the filter register. when switching channels, there is an extra delay in the first conversion of de ad t ime / f clk where dead t ime = 60 when fs[10:0] = 1 or 94 when fs > 1 . at low output data rates, this extra delay has little impact on the value of the settling time. however, at high output data rates, the delay must be considered. table 58 summarizes the output data rate when continuously converting on a single channel and the settling time when switching between channels for a sample of fs[10:0]. when the user selects another channel , the ad7124 - 8 allows the complete settling time to generate the first conversion after the channel change. therefore, the adc automatically operates in zero latency mode when several channels are enabled setting the si ngle_cycle bit has no benefits. when the analog input is constant or a channel change occurs, valid conversions are available at a near constant output data rate. when conversions are being performed on a single channel and a step change occurs on the anal og input, the adc continues to output fully settled conversions if the step change is synchronized with the conversion process. if the step change is asynchronous, one conversion is output from the adc that is not completely settled (see figure 92). analog input adc output fully settled 1/ f adc 13048-102 figure 92 . sinc 3 zero latency operation table 58 . examples of output data rates and the corresponding settling time s for the sinc 3 filter (zero latency) power mode fs[ 10 :0] output data rate (sps) settling time (ms) full power (f clk = 614.4 khz) 1920 3.33 300.15 384 16.67 60.15 320 20 50.15 mid power (f clk = 153.6 khz) 480 3.33 3 00 .61 96 16.67 6 0 .61 80 20 50.61 low power (f clk = 76.8 khz) 240 3.33 3 0 1.22 48 16.67 61.22 40 20 51.22 data sheet ad7124-8 rev. b | page 57 of 91 sequencer the description in the sinc3 filter section is valid when manually switching channels, for example, writing to the device to change channels. when multiple channels are enabled, the on-chip sequencer is automatically used; the device automatically sequences between all enabled channels. in this case, the first conversion takes the complete settling time as listed in table 57. for all subsequent conversions, the time needed for each conversion is also the settling time, but the dead time is reduced to 30. sinc 3 50 hz and 60 hz rejection figure 93 shows the frequency response of the sinc 3 filter when the output data rate is programmed to 50 sps and zero latency is disabled. for the same configuration but with zero latency enabled, the filter response remains the same but the output data rate is 16.67 sps. the sinc 3 filter gives 50 hz 1 hz rejection of 95 db minimum for a stable master clock. ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 255075100125150 frequency (hz) filter gain (db) 13048-103 figure 93. sinc 3 filter response (50 sps output data rate, zero latency disabled or 16.67 sps output data rate, zero latency enabled) figure 94 shows the frequency response of the sinc 3 filter when the output data rate is programmed to 60 sps and zero latency is disabled. for the same configuration but with zero latency enabled, the filter response remains the same but the output data rate is 20 sps. the sinc 3 filter has rejection of 95 db minimum at 60 hz 1 hz, assuming a stable master clock. ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 306090120150 frequency (hz) filter gain (db) 13048-104 figure 94. sinc 3 filter response (60 sps output data rate, zero latency disabled or 20 sps output data rate, zero latency enabled) when the output data rate is 10 sps with zero latency disabled or 3.33 sps with zero latency enabled, simultaneous 50 hz and 60 hz rejection is obtained. the sinc 3 filter has rejection of 100 db minimum at 50 hz 1 hz and 60 hz 1 hz (see figure 95). ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 306090120150 frequency (hz) filter gain (db) 13048-105 figure 95. sinc 3 filter response (10 sps output data rate, zero latency disabled or 3.33 sps output data rate, zero latency enabled) simultaneous 50 hz and 60 hz rejection can also be achieved using the rej60 bit in the filter register. when the sinc filter places a notch a 50 hz, the rej60 bit places a first order notch at 60 hz. the output data rate is 50 sps when zero latency is disabled and 16.67 sps when zero latency is enabled. figure 96 shows the frequency response of the sinc 3 filter with this configura- tion. assuming a stable clock, the rejection at 50 hz and 60 hz (1 hz) is in excess of 67 db minimum. ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 25 50 75 100 125 150 frequency (hz) filter gain (db) 13048-106 figure 96. sinc 3 filter response (50 sps output data rate, zero latency disabled or 16.67 sps output data rate, zero latency enabled, rej60 = 1) fast settling mode (sinc 4 + sinc 1 filter) in fast settling mode, the settling time is close to the inverse of the first filter notch; therefore, the user can achieve 50 hz and/or 60 hz rejection at an output data rate close to 1/50 hz or 1/60 hz. the settling time is approximately equal to 1/output data rate. therefore, the conversion time is near constant when converting on a single channel or when converting on several channels. ad7124-8 data sheet rev. b | page 58 of 91 enable the fast se ttling mode using the filter bits in the f ilter register. in fast settling mode, a sinc 1 filter is included after the sinc 4 filter. the sinc 1 filter averages by 16 in the full po wer and mid power modes and averages by 8 in the low power mode. in figure 97 , the blocks shown in gray are unused . sinc 3 / sinc 4 filter modulator averaging block post filter 13048-107 f igure 97 . fast settling mode, sinc 4 + sinc 1 filter output data rate and settling time, sinc 4 + sinc 1 filter when continuously converting on a single channel, the o utput data rate is f adc = f clk /((4 + av g ? 1) 32 fs[ 10 :0] ) where: f adc is the output data rate . f clk is the master clock frequency (614. 4 khz in full power mode, 153.6 khz in mid power mode , and 76.8 khz in low power mode) . avg is 16 for the full or mid power mode and 8 for low power mode . fs[10:0] is the decimal equivalent of the fs[10:0] bits in the f ilter register. fs[10:0] can have a value from 1 to 2047. when another channel is selected by the user , there is an extra delay in the first conversion . the settling time is equal to t settl e = ((4 + av g ? 1) 32 fs[ 10 :0] + dead t ime )/ f clk where dead t ime = 94. the 3 db frequency is equal to f 3db = 0. 44 f adc table 59 lists sample fs [10:0] setting s and the corresponding output data rates and settling times. table 59 . examples of output data rates and the corresponding settling time s (fast settling mode, sinc 4 + sinc 1 ) power mode fs[10:0] first notch (hz) output data rate (sps) settling time (ms) full power (f clk = 614.4 khz, average by 16) 120 10 8. 42 118.9 24 50 42.11 23.9 20 60 50.53 19.94 mid power (f clk = 153.6 khz, average by 16) 30 10 8.42 119.36 6 50 42.11 24.36 5 60 50.53 20.4 low power (f clk = 76.8 khz, average by 8) 30 10 7.27 138.72 6 50 36.36 28.72 5 60 43.64 24.14 when the analog input is constant or a channel change occurs, valid conversions are available at a near constant output data rate. conversions channe l a channe l channe l b ch a ch a ch a ch a ch a ch b ch b ch b ch b 1/f adc dt/f clk 13048-108 notes 1. dt = dead time. f igure 98 . fast settling, sinc 4 + sinc 1 filter when the device is converting on a single channel and a ste p change occurs on the analog input, the adc does not detect the change and continues to output conversions. if the step change is synchronized with the conversion, only fully settled results are output from the adc. however, if the step change is asynchro nous to the conversion process, there is one intermediate result, which is not completely settled (see figure 99 ). analog input adc output valid 1/ f adc 13048-109 f igure 99 . step change on the analog input, sinc 4 + sinc 1 filter sequencer the descript ion in the fast settling mode (sinc 4 + sinc 1 filter) section is valid when manually switching channels , for example, writing to the device to change channel s . when multiple channels are enabled, the on - chip sequencer is automatica lly used ; the device automatically sequence s between all enabled channels. in this case, the first conversion take s the complete settling time as listed in table 59. for all subsequent conversions, the time ne eded for each conversion is also the settling time, but the de ad time is reduced to 30. 50 hz and 60 hz rejection, sinc 4 + sinc 1 filter figure 100 shows the frequency response when f s[10:0] is set to 24 in the full power mode or 6 in t he mid power mode or low power mode. table 59 lists the corresponding output data rate. the sinc filter places the first notch at f notch = f clk /( 32 fs[ 10:0] ) the sinc 1 filter places notches at f notch /avg (avg equaling 16 for th e full power mode and mid power mode and equaling 8 for the low power mode ) . notches are also placed at multiples of this frequency; therefore, when fs[ 10 :0] is set to 6 in the full power mode or mid power mode , a notch is placed at 800 hz due to the sinc filter and notches are placed at 50 hz and multiples of 50 hz due to the averaging. in low power mode, a notch is placed at 400 hz due to the sinc filter and notches are placed at 50 hz and multiples of 50 hz due to the averaging . the notch at 50 hz is a first - order notch; therefore, the notch is not wide. this means that the rejection at 50 hz exactly is good, assuming a stable master clock. however, in a band of 50 hz 1 hz , the rejection degrades significantly. the rejection at 50 hz 0.5 hz is 40 db minimum , assuming a stable clock; therefore, a good master clock source is recommended when using fast settling mode . data sheet ad7124- 8 rev. b | page 59 of 91 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequenc y (hz) fi l ter gain (db) 13048- 1 10 figure 100 . 50 hz rejection figure 101 shows the filter response when fs[ 10 :0] is set to 20 in full power mode or 5 in the mid power and low power modes. in this case, a notch is placed at 60 hz and multiples of 60 hz . the rejection at 60 hz 0.5 hz is equal to 4 0 db minimum . ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequenc y (hz) fi l ter gain (db) 13048- 11 1 figure 101 . 60 hz re jection simultaneous 50 hz/60 hz rejection is achieved when fs[ 10 :0] is set to 384 in full power mode or 30 in the mid power and low power modes. notches are plac ed at 10 hz and multiples of 10 hz, t hereby giving simultaneous 50 hz and 60 hz rejection. the rejection at 50 hz 0.5 hz and 60 hz 0.5 hz is 44 db typically. ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 frequenc y (hz) fi l ter gain (db) 0 30 60 90 120 150 13048- 1 12 figure 102 . simultaneous 50 hz and 60 hz rejection fast settling mode ( sinc 3 + sinc 1 filter) in fast settling mode, the settling time is close to the inverse of the first filter notch; therefore, the user can achieve 50 hz and/or 60 hz rejection at an output data rate close to 1/50 hz or 1/60 hz. the settling time is approximately equal to 1/output data rate. therefore, the conversion ti me is near constant when c onverting on a single channel or when converting on several channels. enable the fast settling mode using the filter bits in the f ilter register. in fast settling mode, a sinc 1 filter i s included after the sinc 3 filter. the sinc1 filter averages by 16 in the full power and mid power modes and averages by 8 in low power mode. in figure 103 , the blocks shown in gray are unused . s i n c 3 / s i n c 4 f i l t e r m o d u l a t o r a v e r a g i n g b l o c k p o s t f i l t e r 13048- 1 13 figure 10 3 . fast settling mode, sinc 3 + sinc 1 filter output dat a rate and settling time, sinc 3 + sinc 1 filter when continuously converting on a single channel, the output data rate is f adc = f clk /(( 3 + av g ? 1) 32 fs[ 10 :0] ) where: f adc is the output data rate . f clk i s the master clock frequency (614.4 khz in full power mode, 153.6 khz in mid power mode , and 76.8 khz in low power mode). avg is 16 in full or mid power mode and 8 in low power mode. fs[1 0:0] is the decimal equivalent of the fs[10:0] bits in the f ilter register. fs[10:0] can have a value from 1 to 2047. when another channel is selected by the user , there is an extra delay in the first conversion . the settling time is equal to t settle = (( 3 + av g ? 1) 32 fs[10:0] + dead t ime )/ f clk where dead t ime = 94. the 3 db frequency is equal to f 3db = 0.44 f notch table 60 lists some sample fs [10:0] settings and the corresponding output data rates and settling times. table 60 . examples of output data rates and the corresponding settling time s (fast settling mode, sinc 3 + sinc 1 ) power mode fs[10:0] first notch (hz) output data rate (sps) settling time (ms) full power (f clk = 614.4 khz, a verage by 16) 120 10 8.89 112.65 24 50 44.44 22.65 20 60 53.33 18.9 mid power (f clk = 153.6 khz, average by 16) 30 10 8.89 113.11 6 50 44.44 23.11 5 60 53.33 19.36 low power (f clk = 76.8 khz, average by 8) 30 10 8 126.22 6 50 40 26.22 5 60 48 22.06 ad7124-8 data sheet rev. b | page 60 of 91 when the analog input is constant or a channel change occurs, valid conversions are available at a near constant output data rate. conversions channel a channel channel b ch a ch a ch a ch a ch a ch b ch b ch b ch b 1/f adc dt/f clk 13048-114 notes 1. dt = dead time. figure 104. fast settling, sinc 3 + sinc 1 filter when the device is converting on a single channel and a step change occurs on the analog input, the adc does not detect the change and continues to output conversions. when the step change is synchronized with the conversion, only fully settled results are output from the adc. however, if the step change is asynchronous to the conversion process, one intermediate result is not completely settled (see figure 105). analog input adc output valid 1/ f adc 13048-115 figure 105. step change on the analog input, sinc 3 + sinc 1 filter sequencer the description in the fast settling mode (sinc 3 + sinc 1 filter) section is valid when manually switching channels, for example, writing to the device to change channels. when multiple channels are enabled, the on-chip sequencer is automatically used; the device automatically sequences between all enabled channels. in this case, the first conversion takes the complete settling time as listed in table 60. for all subsequent conversions, the time needed for each conversion is also the settling time, but the dead time is reduced to 30 . 50 hz and 60 hz rejection, sinc 3 + sinc 1 filter figure 106 shows the frequency response when fs[10:0] is set to 24 in the full power mode or 6 in the mid power mode or low power mode. table 60 lists the corresponding output data rate. the sinc filter places the first notch at f notch = f clk /(32 fs[10:0] ) the averaging block places notches at f notch /avg (avg equaling 16 for the full power mode and mid power mode and equaling 8 for the low power mode). notches are also placed at multiples of this frequency; therefore, when fs[10:0] is set to 6 in full power mode or mid power mode, a notch is placed at 800 hz due to the sinc filter and notches are placed at 50 hz and multiples of 50 hz due to the averaging. in low power mode, a notch is placed at 400 hz due to the sinc filter and notches are placed at 50 hz and multiples of 50 hz due to the averaging. the notch at 50 hz is a first-order notch; therefore, the notch is not wide. this means that the rejection at 50 hz exactly is good, assum- ing a stable master clock. however, in a band of 50 hz 1 hz, the rejection degrades significantly. the rejection at 50 hz 0.5 hz is 40 db minimum, assuming a stable clock; therefore, a good master clock source is recommended when using fast settling mode. ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequency (hz) filter gain (db) 13048-116 figure 106. 50 hz rejection figure 107 shows the filter response when fs[10:0] is set to 20 in full power mode or 5 in the mid power and low power modes. in this case, a notch is placed at 60 hz and multiples of 60 hz. the rejection at 60 hz 0.5 hz is equal to 40 db minimum. ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequency (hz) filter gain (db) 13048-117 figure 107. 60 hz rejection simultaneous 50 hz/60 hz rejection is achieved when fs[10:0] is set to 384 in full power mode or 30 in the mid power and low power modes. notches are placed at 10 hz and multiples of 10 hz, thereby giving simultaneous 50 hz and 60 hz rejection. the rejection at 50 hz 0.5 hz and 60 hz 0.5 hz is 42 db typically. data sheet ad7124- 8 rev. b | page 61 of 91 ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 30 60 90 120 150 frequenc y (hz) fi l ter gain (db) 13048- 1 18 figure 108 . simultaneous 50 hz and 60 hz rejection post filters the post filters provide rejection of 50 hz and 60 hz simultaneously an d allow the user to trade off settling time and rejection. these filters can operate up to 27.27 sps or can reject up to 90 db of 50 hz 1 hz and 60 hz 1 hz interference. these filters are realized by post filtering the output of the sinc 3 filter. the f ilter bits must be set to all 1s to enable the post filter. the post filter option to use is selected using the post_filter bits in the f ilter register. in figure 109 , the blocks shown in gray are unused . sinc 3 / sinc 4 f i l t e r m o d u l a t o r a v e r a g i n g b l o c k p o s t f i l t e r 13048- 1 19 figure 109 . post filters table 61 shows the output data rates with the accompanying settling time s and the r ejection. when continuously converting on a single channel, the first conversion requir es a tim e of t settle . subsequent conversions occur at 1/f adc . when multiple channels are enabled (either manually or using the sequencer) , the settling time is required to generate a valid conversion on each enabled channel. table 61. ad7124 -8 post filters: output data rate, settling time (t settle ) , and rejection output data rate ( sps ) f 3db (hz) t settle , full power mode (ms) t settle , mid power mode (ms) t settle , low p ower mode (ms) simultaneous rejection of 50 hz 1 hz and 60 hz 1 hz (db) 1 27.27 17.28 38.498 38.998 39.662 47 25 15.12 41.831 42.331 42.995 62 20 13.38 51.831 52.331 52.995 86 16.67 12.66 61.831 62.331 62.995 92 1 stable master clock used. ad7124- 8 data sheet rev. b | page 62 of 91 0 ?100 0 600 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 200 300 400 500 13048-120 figure 110 . dc to 600 hz, 27.27 sps output data rate, 36.67 ms settling time 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 13048-121 figure 111 . zoom in 40 hz to 70 hz, 27.27 sps output data rate , 36.67 ms settling time 0 ?100 40 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 600 100 200 300 400 500 13048-122 figure 112 . dc to 600 hz, 25 sps output data rate , 40 ms settling time 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 13048-123 figure 113 . zoom in 40 hz to 70 hz, 25 sps output data rate, 40 ms settling time 0 ?100 0 600 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 200 300 400 500 13048-124 figure 114 . dc to 600 hz, 20 sps output data rate , 50 ms settling time 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 13048-125 figure 115 . zoom in 40 hz to 70 hz, 20 sps output data rate, 50 ms settling time data sheet ad7124- 8 rev. b | page 63 of 91 0 ?100 0 600 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 100 200 300 400 500 13048-126 figure 116 . dc to 600 hz,16.667 sps output data rate , 60 ms settling time 0 ?100 40 70 filter gain (db) frequency (hz) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 45 50 55 60 65 13048-127 figure 117 . zoom in 40 hz to 70 hz, 16.667 sps output data rate , 60 ms settling time ad7124-8 data sheet rev. b | page 64 of 91 summary of filter options the ad7124-8 has several filter options. the filter that is chosen affects the output data rate, settling time, the rms noise, the stop band attenuation, and the 50 hz and 60 hz rejection. table 62 shows some sample configurations and the corresponding performance in terms of throughput and 50 hz and 60 hz rejection. table 62. filter summary 1 filter power mode output data rate (sps) rej60 50 hz rejection (db) 2 sinc 4 all 10 0 all 50 0 all 50 1 all 60 0 120 db (50 hz and 6 0 hz) 1 20 db (50 hz o nl y) 82 db (50 hz and 60 hz) 120 db (60 hz o nl y) sinc 4 , zero latency all 12.5 0 120 db (50 hz only) all 12.5 1 82 db (50 hz and 60 hz) all 15 0 120 db (60 hz only) sinc 3 all 10 0 100 db (50 hz and 60 hz) all 50 0 95 db (50 hz only) all 50 1 67 db (50 hz and 60 hz) all 60 0 95 db (60 hz only) fast settling (sinc 4 + sinc 1 ) full/mid 50.53 0 40 db (60 hz only) l ow 43.64 0 40 db (60 hz only) f ull/mid 42.11 0 40 db (50 hz only) l ow 36.36 0 40 db (50 hz only) f ull/mid 8.4 0 40 db (50 hz and 60 hz) l ow 7.27 0 40 db (50 hz and 60 hz) fast settling (sinc 3 + sinc 1 ) full/mid 53.33 0 40 db (60 hz only) l ow 48 0 40 db (60 hz only) f ull/mid 44.44 0 40 db (50 hz only) l ow 40 0 40 db (50 hz only) f ull/mid 8.89 0 40 db (50 hz and 60 hz) l ow 8 0 40 db (50 hz and 60 hz) post filter all 27.27 0 47 db (50 hz and 60 hz) all 25 0 62 db (50 hz and 60 hz) all 20 0 85 db (50 hz and 60 hz) all 16.67 0 90 db (50 hz and 60 hz) 1 these calculations assume a stable master clock. 2 for fast settling mode, the 50 hz/60 hz rejection is measured in a band of 0.5 hz around 50 hz and/or 60 hz. for all other mo des, a region of 1 hz around 50 hz and/or 60 hz is used. data sheet ad7124- 8 rev. b | page 65 of 91 diagnostics the ad7124 - 8 has numerous diagnostic funct ions on chip. use t hese features t o ensure ? read/write operations are to valid registers only ? only valid data is written to the on - chip registers ? appropriate decoupling is used on the ldos ? the external reference, if used, is present ? the adc modulator and fi lter a re working within specification s ignal c hain c heck functions such as the reference and power supply voltages can be selected as inputs to the adc. th e ad7124 - 8 can therefore check the vo ltages connected to the device. the ad7124 - 8 also generates an internal 20 mv signal that can be applied internally to a channel b y selecting the v_20mv _ p to v_20 mv _ m channel in the channel re gister. the pga can be checked using this function. as the pga setting is increased, for example, the signal as a pe rcent of the analog input range is reduced by a factor of two. this allows the user to check that the pga is functioning correctly. referenc e detect the ad7124 - 8 include s on - chip circuitry to detect if the re is a valid reference for conversions or calibrations when the user selects an external reference as the reference source. th is is a valuable feature in applications such as rtds or strain gages where the reference is derived externally. 0.7v com p ar a t or refin (refinx(+) ? refinx(?)) outpu t : 0 when refin 0.7 1 when refin <0.7 13048-128 figure 118 . reference detect circuitry this feature is enabled when the ref_det _err_en bit in the e rror _e n register is set to 1. if the voltage between the selected refin x (+) and refin x ( ? ) pins goes below 0. 7 v, o r either the refin x (+) or refin x ( ? ) inputs are open circuit, the ad7124 - 8 detect s that it no l o nger ha s a valid reference . in this case, the ref_det_err bit in the e rror register is set to 1. the err bit in the status register is also set. if the ad7124 - 8 is performing normal conversio ns and the ref_det_err bit becomes active, the conversion results revert to all 1s. therefore, it is not necessary to continuously monitor the status of the ref_det_err bit when performing conversions. it is only necessary to verify its status if the conve rsion result read from the adc data register is all 1s. if the ad7124 - 8 is performin g either offset or full - scale calibrations and the ref_det_err bit becomes active, the updating of the resp ective calibration register is inhibited to avoid loading incorrect coefficients to the register , and the ref_det_err bit is set. if the user is concerned about verifying that a valid reference is in place every time a calibration is performed, check the s tatus of the ref_det_ err bit at the end of the calibration cycle. the reference detect flag may be set when the device exits of standby mode. therefore, read the e rror register after exiting standby mode to reset t he flag to 0. calibration, convers ion , an d saturation errors the conversion process and calibration process can also be monitored by the ad7124 - 8 . these diagnostics check the analog input used as well as the modulator and digital fil ter during conversions or calibration. the functions can be enabled using the adc_cal_err_en, adc_conv_err_en , and adc_sat_err_en bits in the e rror _en register. with these functions enabled, the adc_ cal_err, adc_conv_err , and adc_sat_err bits are set if a n error occurs. the adc_conv_err flag is set if there is an overflow or underflow in the digital filter. the adc conversion clamp s to all 0s or all 1s also. this flag is updated in conjunction with the update of the data register and can be cleared only by a read of the error register. the adc_sat_err flag is set if the modulator outputs 20 consecutive 1s or 0s. this indicates that the modulator has saturated. when an offset calibration is performed, the resulting offset coefficient must be between 0x7ffff f and 0xf80000. if the coefficient is outside this range, the offset register is not updated and the adc_cal_err flag is set. during a full - scale calibration , overflow of the digital filter is checked. if an overflow occurs, the error flag is set and the g ain register is not updated. overvoltage/undervol tage detection the overvoltage/undervoltage monitors check the absolute voltage on the ainx analog input pins . the absolute voltage must be within specification to meet the datasheet specifications. if the a dc is operated outside the datasheet limits, linearity degrade s. ainx ove r volt age com p ar a t or av dd + 40mv ainx_ov_err: set if ainx is 40mv above a v dd ainx_uv_err: set if ainx is 40mv above a v ss unde r volt age com p ar a t or note: ainx is ain p or ainm a v ss ? 40mv 13048-129 figure 119 . analog input overvoltage/undervoltage monitors ad7124- 8 data sheet rev. b | page 66 of 91 the positive (ainp) and negative (ain m) analog inputs can be separately checked for overvoltages and u ndervoltages. the ainp_ov_err_en and ainp_uv_err_en bits in the e rror _e n register enable the overvoltage/undervoltage diagnostics respectively. an overvoltage is flagged when the voltage on ainp exceeds av dd while an undervoltage is flagged when the voltag e on ainp goes below av ss . similarly, an overvoltage/undervoltage check on the negative analog input pin is enabled using the ain m _ov_err_en and ain m _ u v_ err_en bits in the e rror_ e n register. the error flags are ain p _ ov_err, ain p _ uv_err, ain m _ ov_err , and a in m _ uv_err in the e rror register. when this function is enabled, the corresponding flags may be set in the e rror register. therefore , the user must read the e rror register when the overvoltage/undervoltage checks are enabled to ensure that the flags are re set to 0. power supply monitor s along with converting external vo ltages, the adc can monitor the voltage on the av dd pin and the io v dd pin . when the input s of av dd to av ss or io v dd to dgnd are selected, the voltage ( av dd t o av ss or iov dd t o dgnd ) is inter nally attenuated by 6, and the resul ting voltage is applied to the - modulator. this is useful because variations in the power supply voltage can be monitored. ldo monitoring there are several ldo checks included on the ad7124 - 8 . like the external power supplies, the voltage generated by the analog and digital ldos are selectable as inputs to the adc. in addition, the ad7124 - 8 ca n continuously monitor the ldo voltages. power supply monitor the voltage generated by the a ldo and d ldo can be monitored by enabl ing the a ldo _ psm _ err _ en bit and the d ldo _ psm _ err _ en bit , respectively , in the error_en register. when enabled, the output vol tage of the ldo is continuously monitored. if the aldo voltage drops below 1.6 v, the aldo_psm_err flag is asserted. if the dldo voltage drops below 1.55 v, the dldo_psm_err flag is asserted. the bit remains set until the corresponding ldo voltage recovers . however, the bit is only cleared when the error register is read. 1.6v ove r vo lt age com p ar a t or aldo set if aldo output vo lt age is less than 1.6v 13048-130 figure 120 . analog ldo monitor 1.55v ove r vo lt age com p ar a t or dldo set if dldo output vo lt age is less than 1.55v 13048-131 figure 121 . digital ldo monitor the ad7 124- 8 can also test the circuitry used for the power supply monitoring. when the aldo_psm_trip_test_en or d ldo_psm_trip_test_en bits are set, the input to the test circuitry is tied to gnd rather than the ldo output. set t he corresponding aldo_psm_err or dldo_psm_err bit. ldo capacitor detect the analog and digital ldos require an external decoupling capacitor of 0.1 f. t h e ad7124 - 8 can check for the presence of this decoupling capacitor. us ing the ldo_cap_chk bits in the error_en register, the ldo be ing checked is turned off and the voltage at the ldo output is monitored. if the voltage falls, this is considered a fail and the ldo_cap_err bit in the e rror register is set. only the analog ld o or digital ldo can be tested for the presence of the decoupling capacitor at any one time. this test also interferes with the conversion process. the circuitry used to check for missing decoupling capacitors can also be tested by the ad7124 - 8 . when the ldo_cap_ chk_test_e n bit in the e rror _e n register is set, the decoupling capacitor is internally disconnected from the ldo, forcing a fault condition. therefore, when the ldo capacitor test is performed, a fault condition is reported , that is, the ldo_cap_err bit in the e rror register is set. mclk counter a stable master clock is important as the output data rate, filter settling time , and the filter notch frequencies are dependent on the maste r clock. the ad7124 - 8 allows the user to monitor the master clock. when the mclk_cnt_en bit in the e rror _e n register is set, the mclk_c ount register increment s by 1 every 131 master clock cycl es. the user can monitor this register over a fixed period of time. the master clock frequency can be determined f rom the re sult in the mclk_count register . the mclk_count register wraps around after it reaches its maximum value. spi sclk counter the spi s clk counter counts the number of sclk pulses used in each read and write operation. cs must frame every read and write operation when this function is used. all read and write operations are multiple s of eight sclk pulses (8, 16, 32, 40, 48). if the sclk counter counts the sclk pulses and the result is not a multiple of eight , an error is flagged ; the spi_sclk_cnt_err b it in the e rror register is set. if a write operation is being performed and the sclk contains an incorrect number of sclk pulses, the value is not written to the addressed register and the write operation is aborted. the sclk counter is enabled by setting the spi_sclk_ cnt_err_en bit in the error_en register. data sheet ad7124- 8 rev. b | page 67 of 91 spi read/write error s along with the sclk counter, the ad7124 - 8 can also check the read and write operations to ensure that valid registers are being addressed. when the spi_read_err_en bit or the spi_ write_err_en bit in the error_en register are set , the ad7124 - 8 checks the address of the read/write operations. if the user attempts to write to or read from any register other than the user registers described in this data sheet, an error is flagged ; the spi_read_err bit or the spi_write_err bit in the error register is set and the read/write operation is aborted. this function , along with the sclk counter and the crc , makes the serial interface more robust. invalid registers are not writt en to or read from. an incorrect number of sclk pulses can cause the serial interface to go asynchronous and incorrect registers to be accessed. the ad7124 - 8 protects against these issues via the diagnostics. spi_i gnore error at certain times, the on - chip registers are not accessible. for example, during power - up, the on - chip registers are set to their default values. the user must wait until this operation is complete before reading from or w riting to registers. also, when offset or gain calibrations are being performed, registers cannot be accessed. the spi_ig n ore_err bit in the error register indicates when the on - chip registers cannot be accessed. this diagnostic is enabled by default. the function can be disabled using the spi_ignore_err_en bit in the error_en register. any read or write operations performed when spi_ignore_err is enabled are ignored. checksum protection the a d7124 - 8 has a checksum mode that can be used to improve interface robustness. using the checksum ensures that only valid data is written to a register and allows data read from a register to be validated. if an error occurs during a register write, the cr c_err bit is set in the error register. however, to ensure that the register write was successful, read back the register and verify the checksum. for crc checksum calcu lations , the following polynomial is always used: x 8 + x 2 + x + 1 the crc_e rr_en bit i n the error_en register enable s and disable s the checksum . the checksum is appended to the end of each read and write transaction. the checksum calculation for the write transaction is calculated using the 8 - bit command word and the 8 - bit to 24 - bit data. f or a read transaction, the checksum is calculated using the command word and the 8 - bit to 32 - bit data output. figure 122 and figure 123 show spi write and read transactions , respectively. 8-bit command 8-bit crc up t o 24-bit input cs data crc cs din sclk 13048-132 figure 122 . spi write transaction with crc 8-bit command 8-bit crc u p t o 32-bit output cmd data crc cs din sclk dout/ rd y 13048-133 figure 123 . spi read transaction with crc if checksum protection is enabled when continuous read mode is active, there is an implied read data command of 0x4 2 before every data transmission that must be accounted for when calculating the checksum value. this ensures a nonzero checksum value even if the adc data equals 0x000000. memory map checksum protection for added robustness, a crc calculati on is performed on the on - chip registers as well . the status register, data register , and mclk counter register are not included in this check as their contents change continuously. the crc is performed at a rate of 1/2400 seconds. each time that the memor y map is accessed, the crc is re calculated. even ts that cause the crc to be re calculated are ? a user write ? a n offset/full - scale calibration ? when the device is operated in single conversion mode and the adc goes into idle mode following the completion of the conversion ? when exiting continuous read mode (the cont_read bit in the adc_c ontrol register is set to 0) the memory map crc function is enabled by setting the mm_crc_err_en bit in the error_en register to 1. if an error occurs, the mm_crc_err bit in the e rror register is set to 1. ad7124- 8 data sheet rev. b | page 68 of 91 crc calculation the checksum, which is 8 bits wide, is generated using the polynomial x 8 + x 2 + x + 1 to generate the checksum, the data is left shifted by eight bits to create a number ending in eight logic 0s. the polynomial is aligned so that its msb is adjacent to the leftmost logic 1 of the data. an xor (exclusive or) function is applied to the data to produce a n ew, shorter number. the polynomial is again aligned so that its msb is adjacent to the leftmost logic 1 of the new result, and the procedure is repeated. this process is repeated until the original data is reduced to a value less than the polynomial. this is the 8 - bit checksum. example of a polynomial crc calculation 24- bit word: 0x654321 ( 8 - bit command and 16 - bit data) an example of generating the 8 - bit checksum using the polynomial based checksum is as follows: initial value 011001010100001100100001 01100101010000110010000100000000 left shifted eight bits x 8 + x 2 + x + 1 = 100000111 polynomial 100100100000110010000100000000 xor result 100000111 polynomial 100011000110010000100000000 xor result 100000111 polynomial 11111110010000100000000 xor result 100000111 polynomial value 1111101110000100000000 xor result 100000111 polynomial value 111100000000100000000 xor result 100000111 polynomial value 1110011 1000100000000 xor result 100000111 polynomial value 1100100100100000000 xor result 100000111 polynomial value 100101010100000000 xor result 100000111 polynomial value 101101100000000 xor result 100000111 polynomial value 1101011000000 xor result 100000111 polynomial value 101010110000 xor result 100000111 polynomial value 1010001000 x or result 100000111 polynomial value 10000110 checksum = 0x86 data sheet ad7124- 8 rev. b | page 69 of 91 burnout currents t he ad712 4 - 8 contain s two constant current generators that can be programmed to 0.5 a, 2 a , or 4 a. one generator sources current from av dd to ain p , and one sinks current from ainm to av ss . these currents enable open wire detection. x-mux a v dd a v ss burnout detect pga1 13048-134 figure 124 . burnout currents the currents are switched to the selected analog input pair. both currents are either o n or off. the burnout bits in the configuration register enable/disable the burnout currents along with setting the amplitude . use t hese curr ents to verify that an external transducer is still operational before attempting to take measurements on that channel. after the burnout currents are turned on, they flow in the external transducer circuit, and a measurement of the input voltage on the an alog input channel can be taken. if the resulting voltage measured is near full scale, the user must verify why this is the case. a near full - scale readin g can mean that the front - end sensor is open circuit. it can also mean that the front - end sensor is ov erloaded and is justified in outputting fu ll scale, or that the refere nce may be absent and the ref_det_err bit is set, thus clamping the data to all 1s. when a conversion is close to full scale , the user must check these three cases before making a judgme nt. if the voltage measured is 0 v, it may indicate that the transducer has short circuited. for normal operation, these burnout currents are turned off by setting the burnout bits to zero. the current sources work over the normal absolute input voltage ra nge specifications with buffers on. temperature sensor embedded in the ad7124 - 8 is a temperature sensor that is useful to monitor the die temperature. this is selected using the ainp [4:0] and ainm [4:0] bits in the channel register . the sensitivity is 13,584 codes/c, approxim ately. the equation for the temperature sensor is temperature (c) = (( conversion ? 0x800000)/13 , 584) ? 272.5 the temperature sensor has an accuracy of 0.5 c typically. ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 ?40 ?30 ?20 ?10 0 15 25 40 50 60 70 85 95 105 temper a ture sensor error (c) temper a ture (c) 32 units 13048-135 figure 125 . temperature sensor error v s. temperatu re ad7124- 8 data sheet rev. b | page 70 of 91 grounding and layout the analog inputs and reference inputs are differential and, therefore, most of the voltages in the analog modulator are common - mode voltages. the high common - mode rejection of the device removes common - mode noise on these inputs. the analog and digital supplies to the ad7124 - 8 are independent and separately pinned out to minimize coupling be tween the analog and digital sections of the device. the digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the master clock frequency. the digital filter also removes noise from the analog and refer ence inputs, provided that these noise sources do not saturate the analog modulator. as a result, the ad7124 - 8 is more immune to noise interference than a conventional high resolution converte r. however, because the resolution of the ad7124 - 8 is high and the noise levels from the converter are so low, care must be taken with regard to grounding and layout. the pcb that houses the a dc must be designed so that the analog and digital sections are separated and confined to certain areas of the board. a minimum etch technique is generally best for ground planes because it results in the best shielding. in any layout, the user must keep i n mind the flow of currents in the system, ensuring that the paths for all return currents are as close as possible to the p aths the currents took to reach their destinations . avoid running digital lines under the device because this couples noise onto the die and allows the analog ground plane to run under the ad7124 - 8 to prevent noise coupling. the power supply lines to the ad7124 - 8 must use as wide a trace as possible to provide low impedance paths and reduce glitches on the power supply line. shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board and never run cloc k signals near the analog inputs. avoid crossover of digital and analog signals. run traces on opposite sides of the board at right angles to each other. this reduces the effects of feedthrough on the board. a microstrip technique is by far the best but is not always possible with a double - sided board. in this technique, the component side of the board is dedicated to ground planes, whereas signals are placed on the solder side. good decoupling is important when using high resolution adcs. the ad7124 - 8 h as two power supply pins av dd and io v dd . the av dd pin is referenced to av ss , and the io v dd pin is ref erenced to dgnd. decouple av dd with a 1 f tantalum capacitor in parallel with a 0.1 f capaci tor to av ss on each pin. place t he 0.1 f capacitor as close as possible to the device on each supply, ideally right up against the device. decouple io v dd with a 1 f tantalum capacitor in parallel with a 0.1 f capaci tor to dgnd. all analog inputs must be decoupled to av ss . if an external reference is used, decouple the ref inx( + ) and ref inx( ? ) pins to av ss . the ad7124 - 8 also has two on - board ldo regulators one that regulates the av dd supply and one that regulates the iov dd supply. for the regcapa pin, it is recommended that a 0.1 f capacitor to av ss be used. similarly, for the regcapd pin, it is recommended that a 0.1 f capacitor to dgnd be used. if using the ad7124 - 8 with split supply operation, a separate plane m ust be used for av ss . data sheet ad7124- 8 rev. b | page 71 of 91 application s information the ad7124 - 8 offer s a low cost, high resolu tion analog - to - digital function. because the analog - to - digital function is provided by a - architecture, the device is more immune to noisy environments, making it ideal for use in sensor measurement, and industrial and process control applications. temperature measurem ent u sing a thermocouple figure 126 outl ines a connection from a thermocouple to the ad7124 - 8 . in a thermocouple application, the voltage generated by the thermocouple is measured with respect to an absolute reference ; thu s, the internal reference is used for this conversion. the cold junction measurement uses a ratiometric configuration , so the reference is provided externally. because the signal from the thermocouple is small, the ad7124 - 8 is operated with the pga enabled to amplify the signal from the thermocouple. as the input channel is buffered, large decoupling capacitors can be placed on the front end to eliminate any noise pickup that may be present in the thermocouple leads. the bias voltage generator provides a common - mode v oltage so that the voltage generated by the thermocouple is biased up to ( av dd ? av ss )/2. for thermocouple voltages that are centered about ground , the ad7124 - 8 can be operated with a split power supply ( 1.8 v). the cold junction compensati on is performed using a thermi s tor i n figure 126 . the on - chip excitation current supplies the thermistor. in addition, the reference voltage for the cold junction measurement is derived from a precision resistor in series with the thermistor. t his allows a ratiometric measurement so that variation of the excitation current has no effect on the measurement (it is the ratio of the precision reference resistance to the thermistor resistance that is measured). most conversions are read from the ther mocouple, with the cold junction being read only periodically as the cold junction temperature is stable or slow moving. if a t - type thermocouple is used, it can measure a temperature from ?200c to +400 c. the voltage generated over this temperature range is ? 8.6 mv to +17.2 mv. the ad7124 - 8 internal reference e quals 2.5 v. therefore, the pga is set to 128. if the thermocouple uses the ain0 / ain1 channel and the thermistor is connected to the a in12 / ain13 channel , the conversion process is as follows : 1. reset the adc . 2. select the power mode . set the channel_ 0 register a nalog i nput to ain0 / ain1. assign setup 0 to this channel. configure setup 0 to have a gain of 128 and select the i nternal r eference. select the filter type and set the output data rate. 3. enable v bias on ain0 . 4. set the channel_ 1 register a nalog i nput to ain12 / ain13 . assign setup 1 to this channel. configure setup 1 to have a gain of 1 and select the e xternal r eference refin2 ( ) . select th e filter type and set the output data rate. 5. enable the excitation current ( ioutx ) and select a suitable value. output this current to the ain4 pin . 6. enable the ain0 / ain1 channel . wait until rdy goes low. read the c onversion . 7. continue to r ead nine further conversions from the ain0/ain1 channel . 8. disable channel_ 0 and enable channel_ 1 . 9. wait until rdy goes low. read one conversion. 10. repeat s tep 5 to step 8. using the linearization equati on for the t - type thermocoupl e , process the thermocouple voltage along with the thermistor voltage and compute the actual temperature at the thermocouple head. seria l inter f ace and contro l logic interna l clock clk av dd av dd ain0 x-mux a v dd reference detect dout/rd y sclk cs iov dd v dd a v ss tem p sensor din sync psw refin1(?) refin1(+) r ref ain1 ain12 ain13 refin2(+) refin2(?) pg a - adc ad7124-8 av ss dgnd v bias diagnostics channe l sequencer band ga p reference notes 1. simplified block diagram shown. regca p a regcapd digi t a l fi l ter r c c r cold junction thermocouple junction 13048-136 figure 126 . thermocouple application ad7124- 8 data sheet rev. b | page 72 of 91 the external anti alias filter is omitted for clarity. however, such a filter is required to reject any interference at the modulator frequency and multiples of the modulator frequency. in addition , some filtering may be needed for emi purposes. both the analo g inputs and the reference inputs can be buffered , which allows th e user to connect any rc combination to the reference or analog input pins. the required power mode depends on the performance required from the system along with the current consumption allowance for the system. in a field transmitter, low current consump tion is essential. in this application, the low power mode or mid power mode is most suitable. in process control applications, power consumption is not a priority. thus , full power mode may be selected. the full power mode offers higher throughput and low er noise. the ad7124 - 8 on - chip diagnostics allow the user to check the circuit connections, monitor power supply, reference , and ldo voltages, check all conversions and calibrations for any er rors , as well as monitor any read/write operations. in thermocouple applications, the circuit connections are verified using the reference detect and the burnout currents. the ref_det_err flag is set if the external reference refin2 ( ) is missing. the burn out current s (available in the c onfiguration registers) detect an open wire. for example, if the thermocouple is not connected and the burnout currents are enabled on the channel, the adc outputs a conversion that is equal to or close to full scale. for be st performance, enable the burnout currents periodically to check the connections but disable them as soon as the connections are verified for they add an error to the conversions. the decoupling capacitors on the ldos can also be checked. t he adc indicate s if the capacitor is not present . as part of the conversion process, the analog input overvoltage/ undervoltage monitors are useful for detect ing any excessive voltages on ain p and ain m. the power supply voltages and reference voltages are se lectable as i nputs to the adc. thus , the user can periodically check these voltages to confirm whether they are within the system specification. also, the user can check that the ldo voltages are within specification. the conversion process and calibration proc ess can also be checked. this e nsures that any invalid conversions or calibrations are flagged to the user. finally, the crc check, sclk counter, and the spi read/write checks make the interface more robust as any read/write operation that is not valid is detected . the crc check highlights i f any bits are corrupted when being transmitted between the processor and the adc. temperature measurem ent u sing an rtd to optimize a 3 - wire rtd configuration, two identically matched current sources are required. the ad7124 - 8 , which contain s two well matched current sources, is ideally suited to these applications. one possible 3 - wire configuration is shown i n figure 127 . in this 3 - wir e configuration, the lead resistances result in errors if only one current (output at ain0) is used, as the excitation current flows through rl1, developing a voltage error between ain1 and ain2. in the scheme ou tlined, the second rtd current source (avail able at ain3) compensate s for the error introduced by the excitation current flowing through rl1. the second rtd current flows through rl2. assuming that rl1 and rl2 are equal (the leads are normally of the same material and of equal length ) and that the e xcitation currents match, the error voltage across rl2 equals the error voltage across rl1, and no error voltage is developed between ain1 and ain2 . twice the voltage is developed across rl3 ; however , because this is a common - mode voltage it does not intro duce errors. the reference voltage for the ad7124 - 8 is also generated using one of the matched current sources. it is developed using a precision resistor and applied to the differential refer ence pins of the adc. this scheme ensures that the analog input voltage span remains ratiometric to the reference voltage. any errors in the analog input voltage due to the temperature drift of the excitation current are compensated by the vari ation of the reference voltage. as an example, the pt100 measures temperature from ?200c to +600c. the resistance is 100 ? typically at 0c and 313.71 ? at 600c. if the 500 a excitation currents are used, the maximum voltage g enerated across the rtd when using th e full temperature range of the rtd is 500 a 313.71 ? = 156.86 mv this is amplified to 2.51 v within the ad7124 - 8 if the gain is programmed to 16. the voltage generated across the refere nce resistor must be at least 2.51 v. therefore, the reference resistor value must equal at least 2.51 v/500 a = 5020 ? therefore, a 5. 11 k? resistor can be used. 5.11 k? excitation current = 5.11 k? 500 a = 2.555 v one other consideration is the out put compliance. the output compliance equals av dd ? 0.3 7 v. i f a 3 .3 v analog supply is used, the volt age at ain0 must be less than (3.3 v ? 0.37 v ) = 2. 93 v. from the previous calculations, this specification is met because the maximum voltage at ain0 equ als the voltage across the reference resistor plus the voltage across the rtd , which equals 2.555 v + 156.86 mv = 2. 712 v data sheet ad7124- 8 rev. b | page 73 of 91 a typical procedure for reading the rtd is as follows: 1. reset the adc . 2. select the power mode . 3. set the channel_ 0 register a nalog i n put to ain1 / ain2. assign setup 0 to this channel. configure setup 0 to have a gain of 16 and select the r eference s ource refin2 () . select the filter type and set the output data rate. 4. progr am the excitation currents to 50 0 a and output the currents on th e ain0 and ain3 pins . 5. wait until rdy goes low. read the conversion value . 6. repeat step 4. in the processor, implement the linearization rout ine for the pt100 . the external an ti alias filter is omitted for clarity. however, such a filter i s required to reject any interference at the modulator frequency and multiples of the modulator frequency. also, some filtering may be needed for emi purposes. both the analog inputs and reference inputs can be buffered , which allows the user to connect an y rc combination to the reference or analog input pins. on the ad7124 - 8 , the excitation currents can be made available at the input pins, for example, the ain 3 pin can function as an analog in put as well as outputting the current source. this option allows multiple sensors to be connected to the adc using a minimum pin count. ho wever, the resistor of the anti aliasing filter is in series with the rtd. this introduces an error in the conversions as there is a vo ltage generated across the anti aliasing resistor. to minimize the error, minimize the resistance of the anti aliasing filter. the power mode to use depends on the performance required from the system along with the current consumption allow ance for the system. in a field transmitter, low current consumption is essential. in this application, the low power mode or mid power mode is most suitable. in process control applications, power consumption is not a priority. thus, full power mode may b e selected. the full power mode offers higher throughput and lower noise. the ad7124 - 8 on - chip diagnostics allow the user to check the circuit connections, monitor the power supply, reference, and ldo voltages, check all conversions and calibrations for any errors, as well as monitor any read/write operations. in rtd applications, the circuit connections are verified using the reference detect and the burnout currents. the ref_det_err flag is s et if the external reference refin2() is missing. the burnout currents (available in the configuration registers) detec t an open wire. the decoupling capacitors on the ldos can also be checked. t he adc indicates if the capacitor is not present . as part of the conversion process, the analog input overvoltage/ undervoltage monitors are useful to detect any excessive voltages on ainp and ainm. the power supply voltages and reference voltages are selectable as inputs to the adc. thus, the user can periodically check these voltages to confirm whether they are within the system specification. also , the user can check that the ldo voltages are within specification. the conversion proces s and calibration process can also be checked. this ensures that any invalid co nversions or calibrations are flagged to the user. finally, the crc check, sclk counter, and the spi read/write checks make the interface more robust as any read/write operation that is not valid is detected. t he crc check highlights if any bits are corrup ted when being transmitted between the processor and the adc . v bias seria l inter f ace and contro l logic interna l clock clk av dd a v dd ain0 x-mux a v dd reference detect dout/rdy sclk cs iov dd v dd a v ss tem p sensor din sync refin1(?) refin1(+) r ref ain1 refin2(+) refin2(?) ain2 ain3 pga - adc ad7124-8 av ss dgnd rtd rl1 rl2 rl3 psw diagnostics channe l sequencer notes 1. simplified block diagram shown. regca p a regcapd digi t al fi l ter 13048-137 figure 127 . 3 - wire rtd application ad7124- 8 data sheet rev. b | page 74 of 91 flowmeter figure 128 shows the ad7124 - 8 being used in a flowmeter application that consists of two pressure transducers, with the rate of flow being equal to the pressure difference. the pressure transducers are arranged in a bridge network and give a differential output volt age between its out+ and out ? terminals. with rated full - scale pressure (in this case , 300 mmhg) on the transducer, the differential output voltage is 3 mv/v of t he input voltage (that is, the voltage between the in + and in ? termi nals). assuming a 3 v exci tation voltage, the full - scale output range from the transducer is 9 mv. the excitation volta ge for the bridge can directly provide the reference for the adc, as the reference input range includes the supply voltage. a second advantage of using the ad7124 - 8 in transducer - based applications is that the low - side power switch can be fully utilized in low power applications. the low - side power switch is connected i n series with the cold side of the bridges. in normal operation, the switch is closed and measurements are taken. in applications where power is of concern, the ad7124 - 8 can be placed in standby m ode, thus significantly reduci ng the power consumed in the application. in addition, the low - side power switch can be opened while in standby mode, thus avoiding unnecessary power consumption by the front - end transducers. when the device is taken out of standby mode, and the low - side p ower switch is closed, the user must ensure that the front - end circuitry is fully settled before attempting a read from the ad7124 - 8 . the power switch can be closed prior to taking the device out of standby, if needed. this allows time for the sensor to power up and settle before the adc powers up and begins sampling the analog input. in the diagram, temperature compensation is performed using a thermistor. the on - chip excitation current suppli es the thermistor. in addition, the reference voltage for the temperature measurement is derived from a precision resistor in series with the thermistor. this allows a ratiometric measurement so that variation of the excitation current has no effect on the measurement (it is the ratio of the precision reference resistance to the thermistor resistance that is measured). if the sensor sensitivity is 3 mv/v and the excitation voltage is 3 v , t he maximum output from the sensor is 9 mv. the ad7124 - 8 pga can be set to 128 to amplify the sensor signal. the ad7124 - 8 pga amplifies the signal to 9 mv 128 = 1.152 v this value does not exce ed the reference voltage (3 v). a typical procedure for reading the sensors is as follows: 1. reset the adc . 2. select the power mode . 3. set the channel_ 0 register a nalog input to ain0 / ain1. assign setup 0 to this channel. configure setup 0 to have a gain of 128 and selec t the r eference s ource to refin1 () . select the filter type and set the output data rate. 4. set the channel_ 1 register a nalog i nput to ain2 / ain3. assign setup 0 to this channel (both channels use the same setup). 5. set the channel_ 2 register a nal og i nput to ain4 / ain5. assign setup 1 to this channel. configure setup 1 to have a gain of 1 and select the r eference source refin2 ( ) . select the filter type and set the output data rate. 6. program the excitation current and output the current on the ain4 p in . 7. enable both channel_ 0 and channel_ 1. enable the data_status bit to identify the channel from which the conversion originated. the adc automatically sequence s through these channels. 8. wait until rdy goes low. read the conversion value . 9. repeat step 8 until the temperature is to be read (every 10 conversions of the pressure sensor readings, for example) . 10. disable channel_ 0 and channel_ 1. enable channel_ 2. 11. wait until rdy goes low. read the conversion. 12. repeat step 6 to step 10. in the processor, the conversion information i s converted to pressure and the flow rate can be calculated. the proc essor typically contains a look up table for each pressure sensor so its variation with temperature can be compensated. the external anti alias filter is omitted for clarity. however, such a filter is required to reject any interference at the modulator frequency and multiples of the modulator frequency. also, some filtering may be needed for emi purposes. both the analog inputs and referenc e inputs can be buffered , which allows the user to connect any rc combination to the reference or analog input pins. the power mode to use depends on the performance required from the system along with the current consumption allowance for the system. in a field transmitter, low current consumption is essential. in this application, low power mode or mid power mode is most suitable. in process control applications, power consumption is not a priority. thus, full power mode may be selected. f ull power mode o ffers higher throughput and lower noise. data sheet ad7124- 8 rev. b | page 75 of 91 the ad7124 - 8 on - chip diagnostics allow the user to check the circuit connections, monitor power supply, reference, and ldo voltages, check all conv ersions and calibrations for any errors, as well as monitor any read/write operations. the ref_det_err flag is set if the external reference refin2() or refin1( ) is missing. the decoupling capacitors on the ldos can also be checked. t he adc indicates if the capacitor is not present . as part of the conversion process, the analog input overvoltage/undervoltage monitors are useful to detect any excessive voltages on ainp and ainm. the power supply voltages and reference voltages are selectable as inputs to t he adc. thus, the user can periodically check these voltages to confirm whether they are within the system specification. in addition , the user can check that the ldo voltages are within specification. the conversion process and calibration process can als o be checked. this ensures that any invalid conversions or calibrations are flagged to the user. finally, the crc check, sclk counter, and the spi read/write checks make the interface more robust as any read/write operation that is not valid is detected. t he crc check highlights i f any bits are corrupted when being transmitted be tween the processor and the adc . v bias seria l inter f ace and contro l logic interna l clock diagnostics channe l sequencer digi t al fi l ter clk av dd ain0 x-mux a v dd a v dd reference detect dout/rd y sclk cs iov dd vdd tem p sensor din sync a v ss notes 1. simplified block diagram shown. a v ss psw out+ out? in+ in? refin1(?) refin1(+) r ref out+ out? in+ in? ain1 ain2 ain3 ain4 ain5 refin2(+) refin2(?) pga - adc ad7124-8 regca p a regcapd a v ss dgnd 13048-138 figure 128 . flowmeter application ad7124- 8 data sheet rev. b | page 76 of 91 on- chip registers the adc is controlled and configured via a number of on - chip registers that are described i n the following sections . in the following description s, set implies a logic 1 state and cleared implies a logic 0 st ate, unless otherwise noted. table 63 . register summary addr . name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 c omms wen r/ w rs [5:0] 0x 00 w 0x00 status rdy error_flag 0 por_flag ch_active 0x 00 r 0x01 adc_ control 0 dout_ rdy _ de l cont_read data_status cs _en ref_en 0x 0000 rw power_mode mode clk_sel 0x02 data data [23:16] 0x 000000 r data [15:8] data [7:0] 0x03 io_ control_1 gpio_dat 4 gpio_dat 3 gpio_dat 2 gpio_dat 1 gpio_ctrl 4 gpio_ctrl 3 gpio_ct rl 2 gpio_ctrl 1 0x000000 rw pdsw 0 iout1 iout0 iout1_ch iout0_ch 0x04 io_ control_2 vbias15 vbias14 vbias1 3 vbias12 vbias11 vbias10 vbias9 vbias8 0x0000 rw vbias 7 vbias6 vbias5 vbias4 vbias3 vbias2 vbias1 vbias0 0x05 id device_id silicon_re vision 0x12 r 0x06 error 0 ldo_cap_err adc_cal_err adc_conv_ err adc_sat_err 0x 000000 r ainp_ov_err ainp_uv_err ainm_ov_err ainm_uv_ err ref_det_err 0 dldo_psm_ err 0 aldo_psm_ err spi_ignore_ err spi_sclk_cnt_ err spi_read_ err spi_write_ err spi _crc_err mm_crc_err 0 0x07 error_en 0 mclk_cnt_en ldo_cap_chk_ test_en ldo_cap_chk adc_cal_err_ en adc_conv_ err_en adc_sat_ err_en 0x 000040 rw ainp_ov_err_ en ainp_uv_err_ en ainm_ov_err_ en ainm_uv_ err_en ref_det_err_ en dldo_psm_ trip_test_en dldo_p sm_ err_en aldo_psm_ trip_test_en aldo_psm_ err_en spi_ignore_ err_en spi_sclk_cnt_ err_en spi_read_ err_en spi_write_ err_en spi_crc_err_en mm_crc_err_ en 0 0x08 mclk_ count mclk_count 0x 00 r 0x09 to 0x18 channel_0 to channel_15 enable setup 0 ainp[4:3] 0x 8001 1 rw ainp[2:0] ainm [4:0] 0x19 to 0x20 config_0 to config_7 0 bipola r burnout ref_bufp 0x 0860 rw ref_bufm ain_bufp ain_bufm ref_sel pga 0x21 to 0x28 filter_0 to filter_7 filter rej60 post_filter single_cycle 0x 060180 rw 0 fs[10:8] fs[7:0] 0x29 to 0x30 offset_0 to offset_7 offset [23:16] 0x 800000 rw offset [15:8] offset [7:0] 0x31 to 0x38 gain_0 to gain_7 gain [23:16] 0x5xxxxx rw gain [15:8] gain [7:0] 1 channel_0 is reset to 0x8001. all other channels are reset to 0x0000. data sheet ad7124- 8 rev. b | page 77 of 91 communications regis ter rs[ 5:0] = 0, 0, 0, 0, 0, 0 the communications register is an 8 - bit , write only register. all communications to the device must start with a write operation to the communications register. the data written to the communi - cations register determines whether th e next operation is a read or write operation, and to which register this operation takes place , the rs [5:0] bits selecting the register to be accessed . for read or write operations, after the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. this is the default state of the interface and, on power - up or after a reset, the adc is in this default state waiting for a write operation to the commu nications register. in situations where the interface sequence is lost, a write operation of at least 64 serial clock cycles with din high returns the adc to this default state by resetting the entire device . table 64 outlines t he bit designations for the communications register. bit 7 denotes the first bit of the data stream. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wen (0) r/ w (0) rs [5:0] (0) table 64. communications register bit descriptions bits bit name description 7 wen write e nable b it. a 0 must be written to this bit so that the write to the communications register actually occurs. if a 1 is the first bit writte n, the device does not clock on to subsequent bits in the register. it stays at this bit location until a 0 is written to this bit. as soon as a 0 is written to the wen bit, the next seven bits are loaded to the communications regist er. 6 r/ w a 0 in this bit location indicates that the next operation is a write to a specified register. a 1 in this position indicates that the next operation is a read from the designated register. 5 : 0 rs [5:0] register a ddress b its. these address bits select which registers of the adc are being selected during this ser ial interface communication. see table 63. status register rs[5:0] = 0, 0, 0, 0, 0, 0 power - on/reset = 0x00 the status register is an 8 - bit , read only register. to access the adc status register, the user must write to the communications register, se lect the next operation to be read, and set the register address bits rs[5:0] to 0 . table 65 outl ines the bit designations for the status register. bit 7 denotes the first bit of the data stream. the number in parentheses indicates the power - on/reset default status of that bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r dy (0) error_flag (0) 0 (0) por_flag (0) ch _active (0) table 65 . status register bit descriptions bits bit name description 7 rdy ready b it for the adc. this bit is c leared when data is written to the adc data register. the rdy bit is set automatically after the adc data register is read or a period of time before the data register is updated with a new conversion result to indicate to the user not to read the conversion data. it is also set when the device is placed in power - down or standby mode . the end of a conversion is also indicated by the dout/ rdy pin. this pin can be used as an alternative to the status register for monitoring the adc for conversion data. 6 error_flag adc e rror b it. this bit i ndicates if one of the error bits has been asserted in the e rror register. this bit is high if one or more of the error bits in the error register has been set. this bit is c leared by a read of the error regist er. 5 0 this bit is set to 0. 4 por_flag power - on r eset f lag. this bit indicates when a power - on reset occurs. a powe r - on reset occurs on power - up, when the power supply voltage goes below a threshold voltage , when a reset is performed , and when comin g out of power - down mode . the status register must be read to clear the bit. ad7124- 8 data sheet rev. b | page 78 of 91 bits bit name description 3 : 0 ch _active these bits indicate which channel is being converted by the adc. 0000 = channel 0 . 0001 = channel 1 . 0010 = channel 2 . 0011 = channel 3 . 0100 = chan nel 4 . 0101 = channel 5 . 0110 = channel 6 . 0111 = channel 7 . 1000 = channel 8 . 1001 = channel 9 . 1010 = channel 10 . 1011 = channel 11 . 1100 = channel 12 . 1101 = channel 13 . 1110 = channel 14 . 1111 = channel 15 . adc_c ontrol register rs[5:0] = 0, 0, 0, 0, 0, 1 power - on/reset = 0x0000 table 66 outlines th e bit designations for the register. bit 15 is the first bit of the data stream. the number in parentheses indicates the power - on/reset default stat us of that bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 (0) 0 (0) 0 (0) d out_ rdy _del (0) cont_read (0) data_status (0) cs _en (0) ref_en (0) power_mode (0) m ode (0) clk_sel (0) table 66. adc control register bit descriptions bits bit name description 15: 13 0 these bits must be programmed with a logic 0 for correct operation. 12 dout_ rdy _del controls the sclk inactive edge to dout/ rdy high time. when dout_ rdy _del is cleared, the delay is 10 ns min imum . when dout_ rdy _del is set, the delay is increased to 1 0 0 ns min imum . this function is useful when cs i s tied low ( the cs _en bit is set to 0). 11 cont_read continuous read of the data register. when this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuou sly read; that is, the contents of the data register are automatically placed on the dout pin when the sclk pulses are applied after the rdy pin goes low to indicate that a conversion is complete. the communications register does not have to be written to for subsequent data reads. to enable continuous read, the cont_read bit is set . to disable continuous read, write a r ead d ata c ommand while the dout/ rdy pin is low. while continuous read is enabled, the adc mo nitors activity on the din line so that it can receive the instruction to disable continuous read. additionally, a reset occurs if 64 consecutive 1s occur on din; therefore, hold din low until an instruction is written to the device. 10 data_status this b it enables the transmission of the status register contents after each data register read. when dat a _sta tus is set, the contents of the status register are transmitted along with each data register read. this function is useful when several channels are se lected because the status register identifies the channel to which the data register value corresponds. 9 cs _en this bit c ontrols when the dout/ rdy pin transitions from being a dout pin to a rdy pin during data read operations. when cs _en is cleared, the dout pin returns to being a rdy pin within n ano s econds of the sclk inactive edge (the delay is determined by the dout_ rdy _del bit ). when set, the dout/ rdy pin continues to operate as a dout pin after the sclk inactive edge. the pin changes function to a rdy pin when cs is taken high. cs _en must be set to use the diagnostic functions spi_write_err, spi_read_err , and spi_sclk_cnt_err. data sheet ad7124- 8 rev. b | page 79 of 91 bits bit name description 8 ref_en internal r eference v oltage e nable. when this bit is set, the internal reference is enabled and available at the refout pin. when this b it is cleared, the internal reference is disabled. 7 : 6 power_mode power mode select. these bits select the power mode. the current consumption and output data rate ranges are dependent on the power mode. 00 = l ow p ower . 01 = m id p ower . 10 = f ull p ower . 11 = f ull p ower . 5 : 2 m ode these bits control the mode of operation for adc. see table 67. 1 : 0 clk_sel these bits select the clock source for the adc. either the on - chip 614.4 khz clock can be used or an external cl ock can be used. the ability to use an external clock allows several ad7124 -8 devices to be synchronized. also, 50 hz and 60 hz rejection is improved when an accurate external clock drives the adc. 00 = i nternal 614.4 khz clock. the i nternal clock is not available at the clk pin. 01 = i nternal 614.4 khz clock. this clock is available at the clk pin. 10 = e xternal 614.4 khz clock . 11 = e xternal clock. the external clock is divided b y 4 within the ad7124 -8 . table 67 . operating modes m ode value description 0000 continuous c onversion m ode ( d efault). in continuous conversion mode, the adc continuous ly performs conversions and places the result in the data register. rdy goes low when a conversion is complete. the user can read these conversions by placing the device in continuous read mode whereby the conversions are automatical ly placed on the dout line when sclk pulses are applied. alternatively, the user can instruct the adc to output the conversion by writing to the communications register. after power - on, a reset, or a reconfiguration of the adc, the complete settling time o f the filter is required to generate the first valid conversion. subsequent conversions are available at the selected output data rate, which is dependent on filter choice. 0001 single c onversion m ode. when single conversion mode is selected, the adc powe rs up and performs a single conversion on the selected channel. the conversion requires the complete settling time of the filter. the conversion result is placed in the da ta register, rdy goes low, and the adc returns to standby mode . the conversion remains in the data register and rdy remains active (low) until the data is read or another conversion is performed. 0010 standby m ode. in standby mode, all sections of the ad7124 - 8 can be powered down except the ldos. the internal reference, on - chip oscillator, low - side power switch , and bias voltage generator can be enabled or disabled while in standby mode. the on - chip registers retain their contents in standby mode. any enabled diagnostics remain active when the adc is in idle mode. the diagnostics can be enabled/disabled while in standby mode. however, any diagnostics that require the master clock (reference detect, undervoltage/overvoltage detecti on, ldo trip tests, memory map crc , and mclk counter) must be enabled when the adc is in continuous conversion mode or idle mode ; these diagnostics do not function if enabled in standby mode. 0011 power - d own m ode. in power - down mode, all the ad7124 - 8 circuitry is powered down , including the current sources, power switch, burnout currents, bias voltage generator, and clock circuitry. the ldos are also powered down. in power - down mode, the on - ch ip registers do not retain their contents. therefore, coming out of power- down mode, all registers must be re programmed. 0100 idle m ode. in idle mode, the adc filter and modulator are held in a reset state even though the modulator clocks continue to be p rovided. 0101 internal z ero -s cale ( o ffset) c alibration. an internal short is automatically connected to the input. rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed i n idle mode following a calibration. the measured offset coefficient is placed in the offset register of the selected channel. select o nly one channel when zero - scale calibration is being performed. an internal zero - scale calibration takes a time of one se ttling period to be performed. 0110 internal f ull -s cale ( g ain) c alibration. a full - scale input voltage is automatically connected to the selected analog input for this calibration. rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mode following a calibration. the measured full - scale coefficient is placed in the gain register of the selected channel. a full - scale calibration is required each time the gain of a channel is changed to minimize the full - scale error. select o nly one channel when full - scale calibration is being performed. an internal full - scale calibration takes a time of one settling period to be performed when the gain is set to 1 and four settling periods for gains greater than one. internal full - scale calibrations cannot be performed in the full power mode. so, if using the full - power mode, select mid or low power mode for the internal full - scale calibration. this calibration is valid in full pow er mode as the same reference and gain are used. when performing internal zero - scale and internal full- scale calibrations, the internal full - scale calibration must be performed before the internal zero - scale calibration. therefore, write 0x800000 to the of fset register before performing any internal full - scale calibration , which resets the offset register to its default value. ad7124- 8 data sheet rev. b | page 80 of 91 m ode value description 0111 system z ero -s cale (offset) c alibration. c onnect the system zero - scale input to the channel input pins of the selected channel. rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mode following a calibration. the measured offset coefficient is placed in the offset register of the select ed channel. a system zero - scale calibration is required each time the gain of a channel is changed. select o nly one channel when full - scale calibration is being performed. a system zero - scale calibration takes a time of one settling period to be performed. 1000 system f ull -s cale (gain) c alibration. c onnect the system full - scale input to the channel input pins of the selected channel. rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mode following a calibration. the measured full - scale coefficient is placed in the gain register of the selected channel. a full - scale calibration is required each time the gain of a channel is changed. select o nly one channel when f ull - scale calibration is being performed. a system full - scale calibration takes a time of one settling period to be performed. 100 1 to1111 reserved . data register rs[5 :0] = 0, 0, 0, 0, 1, 0 power - on/reset = 0x000000 the conversion result from the adc is stored in this data register. this is a read - only register. on completion of a read operation from this register, the rdy bit/pin is set. io_control _1 register rs[5:0] = 0, 0, 0, 0, 1, 1 power - on/reset = 0x000000 table 68 outlines the bit designations for the register. bit 23 is the first bit of the data stream. the number in parenthese s indicates the power - on/reset default status of that bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gpio_dat 4 ( 0) g pio_dat 3 (0) gpio_dat 2 (0) gpio_dat 1 (0) gpio_ctrl4 (0) gpio_ctrl3 (0) gpio_ctrl2 (0) gpio_ctrl1 (0) pdsw (0) 0 (0) iout1 (0) iout0 (0) iout1_ch (0 ) iout0_ch (0 ) table 68. io_c ontrol _1 register bit descriptions bits bit name description 2 3 gpio_dat 4 digital output p 4 . when gpio_ctrl 4 is set, the gpio_dat4 bit sets the value of the p 4 general - purpose output pin. when gpio_dat 4 is high, the p 4 output pin is high. when gpio_dat 4 is low, the p 4 output pin is low. when the io_co ntrol_1 register is read, the gpio_dat 4 bit reflects the status of the p 4 pin if gpio_ctrl 4 is set. 2 2 gpio_dat 3 digital output p 3 . when gpio_ctrl 3 is set, the gpio_dat 3 bit sets the value of the p 3 general - purpose output pin. when gpio_dat 3 is high, the p 3 output pin is high. when gpio_dat 3 is low, the p 3 output pin is low. when the io_control_1 register is read, the gpio_dat 3 bit reflects the status of the p 3 pin if gpio_ctrl 3 is set. 21 gpio_dat2 digital output p2. when gpio_ctrl2 is set, the gpio_dat2 bit sets the value of the p2 general - purpose output pin. when gpio_dat2 is high, the p2 output pin is high. when gpio_dat2 is low, the p2 output pin is low. when the io_control_1 register is read, the gpio_dat2 bit reflects the status of the p2 pin if gpi o_ctrl2 is set. 20 gpio_dat1 digital output p1. when gpio_ctrl1 is set, the gpio_dat1 bit sets the value of the p1 general - purpose output pin. when gpio_dat1 is high, the p1 output pin is high. when gpio_dat1 is low, the p1 output pin is low. when the io_ control_1 register is read, the gpio_dat1 bit reflects the status of the p1 pin if gpio_ctrl1 is set. 1 9 gpio_ctrl 4 digital output p 4 enable. when gpio_ctrl 4 is set, the digital outp ut p4 is active. when gpio_ctrl4 is cleared, the pin fu nctions as analog input pin ain5 . data sheet ad7124- 8 rev. b | page 81 of 91 bits bit name description 1 8 gpio_ctrl 3 digital output p 3 enable. when gpio_ctrl3 is set, the digital output p3 is active. when gpio_ctrl3 is cleared, the pin fu nctions as analog input pin ain4 . 17 gpio_ctrl2 digital output p2 enable. when gpio_ctrl2 is set, the d igital output p2 is active. when gpio_ctrl2 is cleared, the pin functions as analog input pin ain3. 16 gpio_ctrl1 digital output p1 enable. when gpio_ctrl1 is set, the digital output p1 is active. when gpio_ctrl1 is cleared, the pin functions as analog in put pin ain2. 15 pdsw bridge power - down switch control bit. s et t his bit to close the bridge power - down switch pdsw to agnd. the switch can sink up to 30 ma. clear this bit to open the bridge power - down switch. when the adc is placed in standby mode, the bridge power - down switch remains active. 14 0 this bit must be programmed with a logic 0 for correct operation. 13: 11 iout1 these bits set the value of the excitation c urrent for iout1. 000 = o ff . 001 = 50 a . 010 = 100 a 011 = 250 a . 1 00 = 500 a . 101 = 750 a . 110 = 1000 a 111 = 1000 a . 10: 8 iout0 these bits set the value of the excitation c urrent for iout0. 000 = o ff . 001 = 50 a . 010 = 100 a 011 = 250 a . 100 = 500 a . 101 = 750 a . 110 = 1000 a 111 = 1000 a . 7 : 4 iout1_ch channel s elect bits for the excitation current for iout1. 0000 = iout1 is available on the ain0 pin. 0001 = iout1 is available on the ain1 pin. 0010 = iout1 is available on the ain2 pin. 0011 = iout1 is availabl e on the ain3 pin. 0100 = iout1 is available on the ain4 pin. 0101 = iout1 is available on the ain5 pin. 0110 = iout1 is available on the ain6 pin. 0111 = iout1 is available on the ain7 pin. 1000 = iout1 is available on the ain8 pin. 1001 = iout1 is available on the ain9 pin. 1010 = iout1 is available on the ain10 pin. 1011 = iout1 is available on the ain11 pin. 1100 = iout1 is available on the ain12 pin. 1101 = iout1 is available on the ain13 pin. 1110 = iout1 is available on the ain14 pin. 0111 = iout1 is available on the ain15 pin. ad7124- 8 data sheet rev. b | page 82 of 91 bits bit name description 3 : 0 iout0_ch channel s elect bits for the excitation current for iout0. 0000 = iout0 is available on the ain0 pin. 0001 = iout0 is available on the ain1 pin. 0010 = iout0 is availab le on the ain2 pin. 0011 = iout0 is available on the ain3 pin. 0100 = iout0 is available on the ain4 pin. 0101 = iout0 is available on the ain5 pin. 0110 = iout0 is available on the ain6 pin. 0111 = iout0 is available on the ain7 pin. 100 0 = iout0 is available on the ain8 pin. 1001 = iout0 is available on the ain9 pin. 1010 = iout0 is available on the ain10 pin. 1011 = iout0 is available on the ain11 pin. 1100 = iout0 is available on the ain12 pin. 1101 = iout0 is available on the ain13 pin. 1110 = iout0 is available on the ain14 pin. 1111 = iout0 is available on the ain15 pin. io_c ontrol _2 register rs[5:0] = 0, 0, 0, 1, 0, 0 power - on/reset = 0x0000 table 69 outlines the bit designations for the register. bit 15 is the first bit of the data stream. the number in parenthese s indicates the power - on/reset default status of that bit. the internal bias voltage can be enabled on multiple channels. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vbias15 (0) vbias14 (0) vbias13 (0) vbias12 (0) vbias11 (0) vbias10 (0) vbias9 (0) vbias8 (0) vbias7 (0) vbias6 (0) vbias5 (0) vbias4 (0) vbias3 (0) vbias2 (0) vbias1 (0) vbias0 (0) table 69. io_c ontrol _2 register bit descriptions bits bit name description 15 vbias 15 enable the b ias v oltage on the ain 15 channel . when set, the internal bias voltage is available on ain 15. 14 vbias 14 enable the b ias v oltage on the ain 14 channel . when set, the internal bias voltage is available on a in 14. 13 vbias 13 enable the b ias v oltage on the ain 13 channel . when set, the internal bias voltage is available on ain 13. 12 vbias 12 enable the b ias v oltage on the ain 12 channel . when set, the internal bias voltage is available on ain 12. 11 vbias 11 enab le the b ias v oltage on the ain 11 channel . when set, the internal bias voltage is available on ain 11. 10 vbias 10 enable the b ias v oltage on the ain 10 channel . when set, the internal bias volt age is available on ain10 . 9 vbias 9 enable the b ias v oltage on t he ain 9 channel . when set, the internal bias voltage is available on ain 9 . 8 vbias 8 enable the b ias v oltage on the ain 8 channel . when set, the internal bias volt age is available on ain8 . 7 vbias 7 enable the b ias v oltage on the ain 7 channel . when set, the internal bias voltage is available on ain 7 . 6 vbias 6 enable the b ias v oltage on the ain 6 channel . when set, the internal bias volt age is available on ain6 . 5 vbias 5 enable the b ias v oltage on the ain 5 channel . when set, the internal bias voltage is avai lable on ain 5 . 4 vbias4 enable the b ias v oltage on the ain 4 channel . when set, the internal bias volt age is available on ain4 . 3 vbias3 enable the b ias v oltage on the ain3 channel . when set, the internal bias voltage is available on ain3. 2 vbias2 enabl e the b ias v oltage on the ain2 channel . when set, the internal bias voltage is available on ain2. 1 vbias1 enable the b ias v oltage on the ain1 channel . when set, the internal bias voltage is available on ain1. 0 vbias0 enable the b ias v oltage on the ain0 channel . when set, the internal bias voltage is available on ain0. data sheet ad7124- 8 rev. b | page 83 of 91 id register rs[5:0] = 0, 0, 0, 1, 0, 1 power - on/reset = 0x12 the identification number for the ad7124 - 8 is stored in the id register. this is a read only register. error register rs[5:0] = 0, 0, 0, 1, 1, 0 power - on/reset = 0x000000 diagnostics , such as checking overvoltages and checking the spi interface , are included on the ad7124 - 8 . the error register contains the flags for the different diagnostic functions. the functions are enabled and disabled using the error_en register. table 70 outlines the bit designations for the register. bi t 23 is the first bit of the data stream. the number in parenthese s indicates the power - on/reset default status of that bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 (0) ldo_cap_err (0) adc_cal_err (0) adc_conv_err (0) adc_sat_err (0) ainp_ov _err (0) ainp_uv_err (0) ainm_ov_err (0) ainm_uv_err (0) ref_det_err (0) 0 (0) dldo_psm_err (0) 0 (0) aldo_psm_err (0) spi_ignore_err (0) spi_sclk_cnt_err (0) spi_read_err (0) spi_write_err (0) spi_crc_err (0) mm_crc_err (0) 0 (0) table 70. e rror register bit descriptions bits bit name description 23: 20 0 these bits must be programmed with a logic 0 for correct operation. 19 ldo_cap_err analog/ d igital ldo d ecoupling c apacitor c heck. this flag is set if the decoupling capacito rs required for the analog and digital ldos are not connected to the ad7124 - 8 . 18 adc_cal_err calibration c heck. if a calibration is initiated but not completed, this flag is set to indicate that an error occurred during the calibration. the associated calibration register is not updated. 17 adc_conv_err this bit i ndicates whether a conversion is valid. this flag is set if an error occurs during a conversion. 16 adc_ sat _err adc saturation f lag. this flag is set if the modulator is saturated during a conversion. 15 ainp_ov_err over v oltage detect ion on ain p . 14 ainp_uv_err under v oltage detect ion on ain p . 13 ain m _ov_err over v oltage detect ion on ain m . 12 ain m _uv_err under v oltage detect ion on ain m . 11 ref_det_err reference d etect ion . this flag indicates when the external reference being used by the adc is open ci rcuit or less than 0.7 v . 10 0 this bit must be programmed with a logic 0 for correct operation. 9 dldo_psm_err digital ldo e rror . this flag is set if an error is detected with the digital ldo. 8 0 this bit must be programmed with a logic 0 for correct operation. 7 aldo_psm_err analog ldo error . this flag is set if an error is detected with the analog ldo voltage. 6 spi_ign ore_err when a crc check of the internal registers is being performed, the on - chip registers cannot be accessed. user instructions are ignored by the adc. this bit is set when the crc check of the registers is occurring. the bit is cleared when the check i s complete ; read and write operations can only be performed then. 5 spi_sclk_cnt_err all serial communications are some multiple of eight bits. this bit is set when the number of sclk cycles is not a multiple of eight. 4 spi_read_err this bit is set when an error occurs during an spi read operation. 3 spi_write_err this bit is set when an error occurs during an spi write operation. 2 spi_crc_err this bit is set if an error occurs in the crc check of the serial communications. 1 mm_crc_err memory m ap er ror . a crc calculation is performed on the memory map each time that the registers are written to. following this, periodic crc checks are performed on the on - chip registers. if the register contents have changed, the mm_crc bit is set. 0 0 this bit must be programmed with a logic 0 for correct operation. ad7124- 8 data sheet rev. b | page 84 of 91 error_en register rs[5:0] = 0, 0, 0, 1, 1, 1 power - on/reset = 0x000040 all the diagnostic functions can be enabled or disabled by setting the appropriate bits in this register. table 71 outlines the bit designations for the register. bit 23 is the first bit of the data stream. the number in parenthese s indicates the power - on/reset default status of that bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 (0) mclk_cnt_ en (0) ldo_cap_chk_ test_en (0) ldo_cap_chk (0) adc_cal_err_ en (0) adc_conv_err_ en (0) adc_sat_ err_en (0) ainp_ov_ err_en (0) ainp_uv_ err_en (0) ainm_ov_err_ en (0) ainm_uv_ err_en (0) ref_det_err_ en (0) dldo_psm_ trip_test_en (0) dldo_psm_err_ en (0) al do_psm_ trip_test_en (0) aldo_psm_ err_en (0) spi_ignore_ err_en (0) spi_sclk_cnt_ err_en (0) spi_read_ err_en (0) spi_write_ err_en (0) spi_crc_err_ en (0) mm_crc_err_ en (0) 0 (0) table 71 . error_en register bit descriptions bi ts bit name description 23 0 this bit must be programmed with a logic 0 for correct operation. 22 mclk_cnt_en mas ter clock counter. when this bit is set, the master clock counter is enabled and the result is reported via the mclk_count register. the c ounter monitors the master clock being used by the adc. if an external clock is the clock source, the mclk counter monitor s this external clock. similarly, if the on - chip oscillator is selected as the clock source to the adc, the mclk counter monitors the on - chip oscillator. 21 ldo_cap_ chk _test_en test of a nalog/ d igital ldo d ecoupling c apacitor c heck . when this bit is set, the decoupling capacitor is internally disconnected from the ldo, forcing a fault condition. this allows the user to test the circuitry that is used for the analog and digital ldo decoupling capacitor check. 20: 1 9 ldo_cap_ chk analog/ d igital ldo d ecoupling c apacitor c heck . t hese bits enable the capacitor check. when a check is enabled, the adc checks for the presence of the external decou pling capacitor on the selected supply. when the check is complete, the ldo_cap_chk bits are both reset to 0. 00 = c heck is not enabled . 01 = c heck the analog ldo capacitor . 10 = c heck the digital ldo capacitor . 11 = c heck is not enabled . 18 a dc_ cal _err_en when this bit is set, the calibration fail check is enabled. 1 7 adc_ conv _err_en when this bit is set, the conversions are monitored and the adc_conv _err bit is set when a conversion fails. 1 6 adc_sat _err_en when this bit is set, the adc mod ulator saturation check is enabled. 1 5 ainp_ov_err _en when this bit is set, the overvoltage monitor on al l enabled ain p channels is enabled. 1 4 ainp_uv_err _en when this bit is set, the undervolta ge monitor on all enabled ain p channels is enabled. 13 ain m _ov_err _en when this bit is set, the overvoltage monitor on all enabled ain m channels is enabled. 12 ain m _uv_err _en when this bit is set, the undervol tage monitor on all enabled ain m channels is enabled. 11 ref_det_err _en when this bit is set, any exte rnal reference being used by the adc is continuously monitored. an error is flagged i f the external reference is open circuit or has a value of less than 0. 7 v. 10 dldo_psm_trip_test_en checks the test mechanism that monitor s the digital ldo. when this b it is set, the input to the test circuit is tied to d gnd instead of the ldo output. set t he dldo_psm_err bit in the error register. 9 dldo_psm_err _err when this bit is set, the digital ldo voltage is continuously monitored. the dldo_psm_err bit in the er ror register is set if the voltage being output from the digital ldo is outside specification. 8 a ldo_psm_trip_test_en checks the test mechanism that monitor s the analog ldo. when this bit is set, the input to the test circuit is tied to av ss instead of the ldo output. set t he aldo_psm_err bit in the error register. 7 aldo_psm_err _en when this bit is set, the analog ldo voltage is continuously monitored. the aldo_psm_err bit in the error register is set if the voltage being output from the analog ldo is outside specification. 6 spi_ignore_err _en when a crc check of the internal registers is being performed, the on - chip registers cannot be accessed. user instructions are ignored by the adc. set t hi s bit so that the spi_ignore_err bit in the error registe r informs the user when read and write operations must not be performed. data sheet ad7124- 8 rev. b | page 85 of 91 bi ts bit name description 5 spi_sclk_cnt_err _en when this bit is set, the sclk counter is enabled. all read and write operations to the adc are multiples of eight bits. for every serial communication, the scl k counter counts the number of sclk pulses. cs must be used to frame each read and write operation. if the number of sclk pulses used during a communication is not a multiple of eight, the spi_sclk_cnt_err bit in the error register i s set. for example, a glitch on the sclk pin during a read or write operation can be interpreted as an sclk pulse. in this case, the spi_sclk_cnt_err bit is set as there is an excessive number of sclk pulses detected. cs _en in the ad c_ control register must be set to 1 when the sclk counter function is being used. 4 spi_read_err _en when this bit is set, the spi_read_err bit in the error register is set when an error occurs during a read operation. an error occurs if the user attempts to read from invalid addresses. cs _en in the adc_control register must be set to 1 when the spi read check function is being used. 3 spi_write_err _en when this bit is set, the spi_write_err bit in the error register is set when an e rror occurs during a write operation. an error occurs if the user attempts to write to invalid addresses or write to read - only registers. cs _en in the adc_control register must be set to 1 when the spi write check function is being u sed. 2 spi_crc_err _en this bit enables a crc check of all read and write operations. the spi_crc_err bit in the error register is set if the crc check fails. in addition, an 8 - bit crc word is appended to all data read from the ad7124 - 8 . 1 mm_crc_err _en when this bit is set, a crc calculation is performed on the memory map each time that the registers are written to. following this, periodic crc checks are performed on the on - chip registers. if the register contents have changed, the mm_crc bit is set. 0 0 this bit must be programmed with a logic 0 for correct operation. mclk_c ount register rs[5:0] = 0, 0, 1 , 0 , 0 , 0 power - on/reset = 0x00 the master clock frequency can be monitored using t his register . table 72 outlines the bit designations for the register. bit 7 is the first bit of the data stream. the number in parenthese s indicates the power - on/reset default status of that bit. bit 7 bit 6 bit 5 bit 4 bit 3 b it 2 bit 1 bit 0 mclk_count (0) table 72. mclk_count register bit descriptions bits bit name description 7 : 0 mclk_count this register allows the user to determine the frequency of the internal/external oscillator. internally , a clock counter increments every 131 pulses of the sampling clock (614.4 khz in full power mode, 153.6 khz in mid power mode , and 768 khz in low power mode) . the 8 - bit counter wraps around on reaching its maximum value. the counter output is read back via t h is register. ad7124- 8 data sheet rev. b | page 86 of 91 channel register s rs[5:0] = 0, 0, 1 , 0 , 0 , 1 to 0, 1, 1, 0, 0, 0 power - on/reset = 0x 8 00 1 for ch annel_ 0 ; a ll other c hannel registers are set to 0x0001 s ixteen channel registers are includ ed on the ad7124 - 8 , channel_ 0 to channel_ 15. the channel registers begin at a ddress 0x09 ( channel_ 0) and end at a ddress 0x1 8 ( channel_ 15). via each register, the user can configure the channel ( ain p input and ain m input ) , enable or disab le the channel , and select the setup . t he setup is selectable from eight different options defined by the user. when the adc converts, i t automatically sequences through all enabled channels. this allows the user to sample some channels multiple times in a sequence, if required. in addition, it allows the user to include diagnostic functions in a sequence also. table 73 outlines the bit designations for the register. bit 15 is the first bit of the data stream. the number in parent hese s indicates the power - on/reset default status of that bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 e nable ( 1 ) s etup (0) ( 0) 0 (0) ainp[4:3] (00) ainp[2:0] (000) ain m [4:0] (00001) table 73. channel register bit descr iptions bits bit name description 15 e nable channel enable bit. setting this bit enables the device channel for the conversion sequence. by default , only the enable bit for channel 0 is set. the order of conversions starts with the lowest enabled c hanne l, then cycles through successively higher channel numbers, before wrapping around to the lowest channel again. when the adc writes a result for a part icular channel, the four lsbs of the s tatus r egister are set to the channel number, 0 to 15. this allo ws the channel the data corresponds to be identified. when t he data_status bit in the adc_control register is set, the contents of the s tatus register are appended to each conversion when it is read. u se this function when several channels are enabled to determine to which channel the conversion value read corresponds. 14: 12 s etup setup select. these bits identify which of the eight s etups are used to configu re the adc for this channel. a s etup compris es a set of four registers: a nalog c onfiguration, o utput d ata r ate/ f ilter s election, o ffset r egister, and g ain r egister . all channels can use the same s etup, in which case the same 3 - bit value must be written to these bits on all active channels . alternati vely, u p to eight channels can be configured differently. 11: 10 0 th ese bit s must be programmed with a logic 0 for correct operation. 9 : 5 ainp [4:0] positive analog input ain p input select. these bits select which of the analog inputs is connected to the positive input for this channel . 00000 = ain 0 ( d efault) . 00001 = ain 1 . 00010 = ain 2 . 00011 = ain 3 . 00100 = ain 4 . 000101 = ain 5 . 00110 = ain 6 . 00111 = ain 7 . 01000 = ain 8 . 01001 = ain 9 . 01010 = ain 10. 01011 = ain 11 . 011 00 = ain 12. 01101 = ain 13. 01110 = ain 14. 01111 = ain 15. 10000 = t emp erature s ensor . 10001 = av ss . 10010 = internal reference . 10011 = dgnd . 10100 = ( av dd ? av ss )/ 6+. use in conjunction with ( av dd ? av ss )/6? to monitor supply av dd ? av ss . 10101 = ( av dd ? av ss )/ 6?. use in conjunction with ( av dd ? av ss )/6+ to monitor supply av dd ? av ss . 10110 = (iov dd ? dgnd)/6+. use in conjunction with (iov dd ? dgnd)/6 ? to monitor iov dd ? dgnd. 10111 = (iov dd ? dgnd)/6?. use in conjunction wi th (iov dd ? dgnd)/6+ to monitor iov dd ? dgnd. data sheet ad7124- 8 rev. b | page 87 of 91 bits bit name description 11000 = (aldo ? av ss )/6+. use in conjunction with (aldo ? av ss )/6? to monitor the analog ldo. 11001 = (aldo ? av ss )/6?. use in conjunction with (aldo ? av ss )/6+ to monitor the analog ldo. 11010 = (dldo ? dgnd)/6+. use in conjunction with (dldo ? dgnd)/6? to monitor the digital ldo. 11011 = (dldo ? dgnd)/6?. use in conjunction with (dldo ? dgnd)/6+ to monitor the digital ldo. 11100 = v_20mv_p . use in conjunction with v_20mv_m to apply a 20 mv p - p s ignal to the adc. 11101 = v_20mv_m . use in conjunction with v_20mv_p to apply a 20 mv p - p signal to the adc. 10010 = refout . 10011 = dgnd . 4 : 0 ain m[4:0] negative analog input ain m input select. these bits select which of the analog inputs is conn ected to the nega tive input for this channel . 00000 = ain 0 ( d efault) . 00001 = ain 1 . 00010 = ain 2 . 00011 = ain 3 . 00100 = ain 4 . 000101 = ain 5 . 00110 = ain 6 . 00111 = ain 7 . 01000 = ain 8 . 01001 = ain 9 . 01010 = ain 10. 01011 = ain 11. 01100 = ain 12. 01101 = ain 13. 01110 = ain 14 . 01111 = ain 15. 10000 = t emp erature s ensor . 10001 = av ss . 10010 = internal reference . 10011 = dgnd . 10100 = ( av dd ? av ss )/ 6+. use in conjunction with ( av dd ? av ss )/6? to monitor supply av dd ? av ss . 10101 = ( av dd ? av ss )/ 6?. use in conjunction with ( av dd ? av ss )/6+ to monitor supply av dd ? av ss . 10110 = (iov dd ? dgnd)/6+. use in conjunction with (iov dd ? dgnd)/6 ? to monitor iov dd ? dgnd . 10111 = (iov dd ? dgnd)/6?. use in c onjunction with (iov dd ? dgnd)/6 + to monitor iov dd ? dgnd . 11000 = (aldo ? av ss )/6+. use in conjunction with (aldo ? av ss )/6? to monitor the analog ldo. 11001 = (aldo ? av ss )/6?. use in conjunction with (aldo ? av ss )/6+ to monitor the analog ldo. 11010 = (dldo ? dgnd)/6+. use in conjunction with (dldo ? dgnd)/6? to monitor the digital ldo. 11011 = (dldo ? dgnd)/6?. use in conjunction with (dldo ? dgnd)/6+ to monitor the digital ldo. 11100 = v_20mv_p. use in conjunction with v_20mv_m to apply a 20 mv p - p signal to the adc. 11101 = v_20mv_m. use in conjunction with v_20mv_p to apply a 20 mv p - p signal to the adc. 11110 = reserved . 11111 = reserved . ad7124- 8 data sheet rev. b | page 88 of 91 configuration regist er s rs[5:0] = 0, 1, 1 , 0 , 0 , 1 to 1, 0, 0, 0, 0, 0 power - on/res et = 0x08 60 the ad7124 - 8 has eight config uration registers, c onfig _0 to config_ 7 . each config uration register is associated with a setup ; c onfig _x is associated with setup x . in the config urat ion register, the reference source, pola rity, reference buffers enabled or disabled are configured. table 74 outlines the bit designations for the register. bit 15 is the first bit of the data stream. the number in parenthese s in dicates the power - on/reset default status of that bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 (0) b ipolar ( 1 ) b urnout (0) ref_bufp (0) ref_buf m (0) ain_bufp (1) ain_buf m (1) ref_sel (0) pga (0) table 74. config urat ion register bit descriptions bits bit name description 15: 12 0 th ese bit s must be programmed with a logic 0 for correct operation. 11 b ipolar polarity select bit. when this bit is set, b ipolar operation is selected. when this bit is cleared, un ipolar o peration is selected. 10: 9 b urnout these bits select the magnitude of the sensor burnout detect current source. 00 = b urnout current source off (default) . 01 = b urnout current source on, 0.5 a . 10 = b urnout current source on, 2 a . 11 = b urnout current source on, 4 a. 8 ref_bufp buffer enable on refinx(+). when this bit is set, the positive reference input (internal or external) is buffered. when this bit is cleared, the positive refe rence input (internal or external) is unbuffered. 7 ref_buf m buffer enable on refin x ( ? ). when this bit is set, the nega tive reference input (internal or external) is buffered. when this bit is cleared, the nega tive reference input (internal or external) i s unbuffered. 6 ain_bufp buffer enable on ain p . when this bit is set, the selected positive analog input pin is buffered. when this bit is cleared, the selected positive analog input pin is unbuffered. 5 ain_buf m buffer enable on ain m . when this bit is s et, the selected negative analog input pin is buffered. when this bit is cleared, the selected negative analog input pin is unbuffered. 4 : 3 ref_sel reference source select bits. these bits select the reference source to use when converting on any channels using this config uration register. 00 = refin1(+)/refin1( ? ) . 01 = refin2(+)/refin2( ? ) . 10 = i nternal r eference . 11 = av dd . 2 : 0 pga gain select bits. these bits select the gain to use when converting on any channels using this config uration re gister. pga gain input range w hen v ref = 2.5 v (bipolar mode) 000 1 2 .5 v 001 2 1.25 v 010 4 625 mv 011 8 312.5 mv 100 16 156.25 mv 101 32 78.125 mv 110 64 39.06 mv 111 128 19.53 mv data sheet ad7124- 8 rev. b | page 89 of 91 filter register s rs[5:0] = 1 , 0, 0 , 0 , 0 , 1 to 1, 0, 1, 0, 0, 0 power - on/reset = 0x0 60180 the ad7124 - 8 has eight filter registers, filter_ 0 to filter_ 7. each f ilter register is associated with a setup ; filter_x is associated wit h setup x . in the f ilter register, the filter type and output word rate are set. table 75 outlines the bit designations for the register. bit 15 is the first bit of the data stream. the number in parenthese s indicates the power - o n/reset default status of that bit. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 f ilter (0) rej60(0) post_filter (0) single_cycle(0) 0(0) fs[10:8] (0) fs[7:0](0) table 75. filter register bit descriptions bits bit name descr iption 23: 21 f ilter filter type select bits. these bits select the filter type. 000 = s inc 4 f ilter (default) . 001 = r eserved . 010 = s inc 3 f ilter . 011 = r eserved . 100 = f ast s ettling f ilter using the s inc 4 filter. the sinc 4 filter is follow ed by an averaging block , which results in a settling time equal to the conversion time. in full power and mid power modes, averaging by 16 occurs wh ereas averaging by 8 occurs in low power mode. 101 = f ast s ettling f ilter using the s inc 3 filter. the si nc 3 filter is followed by an averaging block , which results in a settling time equal to the conversion time. in full power and mid power modes, averaging by 16 occurs wh ereas averaging by 8 occurs in low power mode. 110 = r eserved . 111 = p ost f ilter e nabled. the ad7124 -8 includes several post filters, selectable using the post_filter bits. the post filters have single cycle settling, the settling time being considerably better than a simp le sinc 3 /sinc 4 filter. these filters offer excellent 50 hz and 60 hz rejection. 20 rej60 when this bit is set, a first order notch is placed at 60 hz when the first notch of the sinc filter is at 50 hz. this allows simultaneous 50 hz and 60 hz rejection. 19: 17 post_filter post filter type select bits. when the filter bits are set to 1, the sinc 3 filter is followed by a post filter that offers good 50 hz and 60 hz rejection at output data rates that have zero latency approximately . post_filter output d ata rate (sps) rejection at 50 hz and 60 hz 1 hz (db) 000 reserved not applicable 010 reserved not applicable 010 27.27 47 011 25 62 100 reserved not applicable 101 20 86 110 16.7 92 111 reserved not applicable 16 single_cycle si ngle cycle conversion enable bit. when this bit is set, the ad7124 -8 settles in one conversion cycle so that it functions as a zero latency adc. this bit has no e ffect when multiple analog inp ut channels are enabled or when the single conversion mode is selected. when the fast filters are used, this bit has no effect. 1 5 : 11 0 th ese bit s must be programmed with a logic 0 for correct operation. 10: 0 fs [10:0] filter output data rate select bits. these bits set the output data rate of the sinc 3 filter, sinc 4 filter , and fast settling filters . in addition, they affect the position of the first notch of the sinc filter and the cutoff frequency. in association with the gain selection, they also deter mine the output noise and, therefore, the effective resolution of the device (see noise tables ). fs can have a value from 1 to 2047. ad7124- 8 data sheet rev. b | page 90 of 91 offset register s rs[5:0] = 1, 0, 1, 0, 0, 1 to 1, 1, 0, 0, 0, 0 power - on/reset = 0x800 00 0 the ad7124 - 8 has eight offset registers, offset_ 0 to offset_ 7. each o ffset register is associated with a setup ; offset_x is associated with setup x . the offset register s are 24 - bit register s and hold the offset calibrat ion coefficient for the adc and its power - on reset valu e is 0x800000 . each of these registers is a read/write register. th es e register s are used in conjunction with the associated gain register to form a register pair. the power - on reset value is automatic ally overwritten if an interna l or system zero - scale calibration is initiated by the us er. the adc must be placed in standby mode or idle mode when writing to the offset register s. gain register s rs[5 :0] = 1, 1, 0, 0, 0 , 1 to 1, 1, 1, 0, 0, 0 power - on/re set = 0x5 xxxxx the ad7124 - 8 has eight gain registers, gain_ 0 to gain_ 7. each g ain register is associated with a setup ; gain_x is associated with setup x . the gain register s are 24- bit registe r s and hold the full - scale calibr ation coefficient for the adc . the ad7124 - 8 is factory calibrated to a gain of 1. the gain register contains this factory generated value on power - on and after a reset . the gain registers are read/write registers. however , when writing to the registers, the adc must be placed in standby mode or idle mode. the default value is automatically overwritten if an internal or system full - scale calibration is initiated by the user or the full - scale register s are written to. data sheet ad7124- 8 rev. b | page 91 of 91 outline dimensions 08-16-2010-b 1 0.50 bsc bot t om view top view pin 1 indic a t or 32 9 16 17 24 25 8 exposed pa d pin 1 indic a t or sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min * 3.75 3.60 sq 3.55 * compliant to jedec standards mo-220- whhd-5 with the exception of the exposed pad dimension. figure 129 . 32 - lead lead frame chip scale package [ lfcsp_wq ] 5 mm x 5 mm body, very, very thin quad (cp - 32 - 12 ) dimensions shown in millimeters order ing guide model 1 temperature range package description package option ad7124 -8 bcp z ? 40c to +1 0 5c 32- lead lead frame chip scale package [lfcsp_wq] cp -32-1 2 ad7124 -8b cp z -rl ? 40c to +1 0 5c 32- lead lead frame chip scale package [lfcsp_wq] cp -32-1 2 ad7124 - 8bcpz - rl7 ? 40c to +1 0 5c 32- lead lead frame chip scale package [lfcsp_wq] cp -32-12 eval - ad7124- 8sdz evaluation board eval - sdp - cb1z evaluation controller board 1 z = rohs compliant p art. ? 2015 analog devices, inc . all rights reserved. trademarks and registered trademarks are the property of their respective owners. d13048 - 0- 7/15(b) |
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